3D integrated circuit device fabrication with precisely controllable substrate removal

• US 8,129,256 B2
• Filed: 08/19/2008
• Issued: 03/06/2012
• Est. Priority Date: 08/19/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Farooq, Mukta G., Hannon, Robert, Iyer, Subramanian S., Koester, Steven J., Purushothaman, Sampath, Yu, Roy R.
• Primary Examiner(s): TRAN, LONG K
• Application Number:
  US12/194,065
• Publication Number:
  US 20100044826A1
• Time in Patent Office: 1,295 Days
• Field of Search: 438/455, 438/622, 438/128, 257/E21.502, 257/E21.503
• US Class Current: 438/455
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

Claims

1. A method for fabricating a 3D integrated circuit, the method comprising the steps of:

providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias;

providing a first active circuitry layer wafer comprising a P+ portion covered by a P−

layer, the P−

layer of the first active circuitry layer wafer including active circuitry and through-silicon vias;

fabricating a second wiring layer at a top surface of the first active circuitry layer wafer;

performing a high-precision face-to-face alignment of the first active circuitry layer wafer face down to the interface wafer;

bonding the second wiring layer of the first active circuitry layer wafer directly to the first wiring layer of the interface wafer;

after bonding the first active circuitry layer wafer to the interface wafer, selectively removing the P+ portion of the first active circuitry layer wafer with respect to the P−

layer of the first active circuitry layer wafer;

after selectively removing the P+ portion of the first active circuitry layer wafer, fabricating a third wiring layer on the backside of the P−

layer;

providing a second active circuitry layer wafer comprising a P+ portion covered by a P−

layer, the P−

layer of the second active circuitry layer wafer including active circuitry;

fabricating a fourth wiring layer at a top surface of the second active circuitry layer Wafer;

performing a high-precision face-to-face alignment of the second active circuitry layer wafer face down to the P−

layer of the first active circuitry layer wafer;

bonding the fourth wiring layer of the second active circuitry layer wafer directly to the third wiring layer on the backside of the P−

layer;

after bonding the second active circuitry layer wafer to the third wiring layer, selectively removing the P+ portion of the second active circuitry layer wafer with respect to the P−

layer of the second active circuitry layer wafer;

after selectively removing the P+ portion of the second active circuitry layer wafer, fabricating a fifth wiring layer on the backside of the P−

layer of the second active circuitry layer wafer;

providing a base wafer, the base wafer including a sixth wiring layer;

performing a high-precision face-to-face alignment of the P−

layer of the second active circuitry layer wafer face down to the base wafer;

bonding the fifth wiring layer on the backside of the P−

layer of the second active circuitry layer wafer directly to the sixth wiring layer of the base wafer; and

after bonding the fifth wiring layer to the base wafer, thinning the interface wafer so as to form an interface layer, and forming metallizations comprising solder bumps on the interface layer, the solder bumps being coupled through the through-silicon vias in the interface layer to the first wiring layer,

wherein the interface wafer is formed of a material that is not soluble in an etchant used in the selectively removing step to selectively etch the P+ portion of the first active circuitry layer wafer with respect to the P−

layer of the first active circuitry layer wafer.

2. A method for fabricating a 3D integrated circuit structure, the method comprising the steps of:

providing a first active circuitry layer wafer comprising a P+ portion covered by a P−

layer, the P−

layer of the first active circuitry layer wafer including active circuitry;

fabricating a first wiring layer at a top surface of the first active circuitry layer wafer;

performing a high-precision face-to-face alignment of the first active circuitry layer wafer face down to an interface wafer that includes a second wiring layer;

bonding the first wiring layer of the first active circuitry layer wafer directly to the second wiring layer of the interface wafer;

after bonding the first active circuitry layer wafer to the interface wafer, selectively removing the P+ portion of the first active circuitry layer wafer with respect to the P−

layer of the first active circuitry layer wafer; and

after selectively removing the P+ portion of the first active circuitry layer wafer, fabricating a third wiring layer directly on the backside of the P−

layer.

3. The method of claim 2, further comprising the steps of:

providing a base wafer, the base wafer including a fourth wiring layer;

performing a high-precision face-to-face alignment of the P−

layer of the first active circuitry layer wafer face down to the base wafer; and

bonding the third wiring layer on the backside of the P−

layer of the first active circuitry layer wafer directly to the fourth wiring layer of the base wafer.

4. The method of claim 3, further comprising the step of:

after bonding the third wiring layer on the backside of the P−

layer of the first active circuitry layer wafer to the base wafer, thinning the interface wafer so as to form an interface layer, and forming metallizations on the interface layer, the metallizations being coupled through vias in the interface layer to the second wiring layer.

5. The method of claim 3, wherein the base wafer includes logic circuitry.

6. The method of claim 2, wherein the interface wafer is formed of a material that is not soluble in an etchant used in the selectively removing step to selectively etch the P+ portion of the first active circuitry layer wafer with respect to the P−

layer of the first active circuitry layer wafer.

7. The method of claim 2, wherein the first active circuitry layer wafer further comprises through-silicon vias.

8. The method of claim 2,

wherein the interface wafer comprises a lightly doped N−

or P−

silicon, and

the performing step comprises performing an infrared alignment.

9. The method of claim 2, wherein the performing step comprises performing a high-precision optical alignment.

10. The method of claim 9, wherein the bonding step comprises bonding the first wiring layer of the first active circuitry layer wafer directly to the second wiring layer of the interface wafer through at least one of copper-copper, copper alloy-copper alloy, and nickel-gold alloy-nickel-gold alloy bonding.

11. The method of claim 2, wherein the bonding step comprises utilizing metal-metal bonding to bond the first wiring layer of the first active circuitry layer wafer directly to the second wiring layer of the interface wafer.

12. The method of claim 2, wherein the providing step comprises the sub-steps of:

epitaxially growing the P−

layer on the P+ portion of the first active circuitry layer wafer; and

fabricating active circuitry in the P−

layer of the first active circuitry layer wafer.

13. The method of claim 2,

wherein the first active circuitry layer wafer is not a temporary handle wafer, and

in the bonding step, neither the first active circuitry layer wafer nor the interface wafer is attached to a temporary handle wafer.

14. The method of claim 2, wherein the first wiring layer of the first active circuitry layer wafer does not include large capture pads, and the second wiring layer of the interface wafer does not include large capture pads.

15. The method of claim 2, further comprising the steps of:

providing another active circuitry layer wafer comprising a P+ portion covered by a P−

layer, the P−

layer of the other active circuitry layer wafer including active circuitry;

fabricating a fourth wiring layer at a top surface of the other active circuitry layer wafer;

performing a high-precision face-to-face alignment of the other active circuitry layer wafer face down to the P−

layer of the first active circuitry layer wafer;

bonding the fourth wiring layer of the other active circuitry layer wafer directly to the third wiring layer on the backside of the P−

layer of the first active circuitry layer wafer;

after bonding the other active circuitry layer wafer, selectively removing the P+ portion of the other active circuitry layer wafer with respect to the P−

layer of the other active circuitry layer wafer; and

after selectively removing the P+ portion of the other active circuitry layer wafer, fabricating another wiring layer directly on the backside of the P−

layer of the other active circuitry layer wafer.

16. The method of claim 15, further comprising the steps of:

providing a base wafer, the base wafer including a base wafer wiring layer;

performing a high-precision face-to-face alignment of a P−

layer of a final active circuitry layer wafer face down to the base wafer; and

bonding a wiring layer on a backside of the P−

layer of the final active circuitry layer wafer directly to the base wafer wiring layer of the base wafer.

17. The method of claim 15, further comprising the steps of:

providing a further active circuitry layer wafer comprising a P+ portion covered by a P−

layer, the P−

layer of the further active circuitry layer wafer including active circuitry;

fabricating a further wiring layer at a top surface of the further active circuitry layer wafer;

performing a high-precision face-to-face alignment of the further active circuitry layer wafer face down to the P−

layer of the previous active circuitry layer wafer;

bonding the further wiring layer of the further active circuitry layer wafer directly to the wiring layer on the backside of the P−

layer of the previous active circuitry layer wafer;

after bonding the further active circuitry layer wafer, selectively removing the P+ portion of the further active circuitry layer wafer with respect to the P−

layer of the further active circuitry layer wafer; and

after selectively removing the P+ portion of the further active circuitry layer wafer, fabricating another wiring layer directly on the backside of the P−

layer of the further active circuitry layer wafer.

18. The method of claim 17, further comprising the step of:

repeating N times the steps of providing a further active circuitry layer wafer, fabricating a further wiring layer, performing a high-precision face-to-face alignment, bonding the further wiring layer of the further active circuitry layer wafer, selectively removing the P+ portion of the further active circuitry layer wafer, and fabricating another wiring layer directly on the backside of the P−

layer of the further active circuitry layer wafer.