High performance system-on-chip discrete components using post passivation process

• US 8,129,265 B2
• Filed: 02/18/2005
• Issued: 03/06/2012
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): GRAYBILL, DAVID E
• Application Number:
  US11/062,277
• Publication Number:
  US 20050170634A1
• Time in Patent Office: 2,573 Days
• Field of Search: None
• US Class Current: 438/622
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03914 the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1146 : Plating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16265 : the item being a discrete passive component
• CPC Class Codes: H01L 2224/29124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/29166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/29171 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48 : of an individual wire connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 : Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. A method of forming an integrated circuit chip, comprising:

providing a silicon substrate, a transistor in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, and a passivation layer over said silicon substrate, over said first metallization structure and over said dielectric layer, wherein an opening in said passivation layer is over a contact point of said first metallization structure, and said contact point is at a bottom of said opening in said passivation layer, wherein said passivation layer comprises a nitride;

forming a second metallization structure on said contact point and over said passivation layer, wherein said forming said second metallization structure comprises forming a glue layer, next forming a seed layer on said glue layer, next forming a photoresist layer on said seed layer, wherein an opening in said photoresist layer exposes a region of said seed layer, next electroplating a first copper layer on said region, next forming a nickel layer over said first copper layer in said opening in said photoresist layer, next removing said photoresist layer, and then removing said seed layer and said glue layer not under said first copper layer; and

mounting a discrete passive component over said second metallization structure, wherein said discrete passive component is connected to said contact point through said second metallization structure.

2. The method of claim 1, wherein said mounting said discrete passive component comprises mounting a discrete inductor over said second metallization structure.

3. The method of claim 1, wherein said mounting said discrete passive component comprises mounting a discrete capacitor over said second metallization structure.

4. The method of claim 1, wherein said mounting said discrete passive component comprises mounting a discrete resistor over said second metallization structure.

5. The method of claim 1, after said forming said second metallization structure, further comprising forming a solder on said second metallization structure, followed by said mounting said discrete passive component further to said solder, wherein said discrete passive component is connected to said second metallization structure through said solder.

6. The method of claim 1, after said forming said second metallization structure, further comprising screen printing a solder on said second metallization structure, followed by said mounting said discrete passive component further to said solder, wherein said discrete passive component is connected to said second metallization structure through said solder.

7. The method of claim 1, wherein said forming said glue layer comprises sputtering a titanium-containing layer.

8. The method of claim 1 further comprising said electroplating said first copper layer with a thickness between 3 and 20 micrometers.

9. The method of claim 1, wherein said forming said nickel layer comprises an electroplating process.

10. The method of claim 1, wherein said forming said glue layer comprises sputtering a titanium-tungsten-alloy layer.

11. The method of claim 1, wherein said forming said glue layer comprises sputtering a chromium-containing layer.

12. The method of claim 1, wherein said forming said seed layer comprises sputtering a second copper layer on said glue layer.

13. The method of claim 1 further comprising said forming said nickel layer with a thickness between 0.1 and 3 micrometers.

14. The method of claim 1 further comprising providing a layer of benzocyclobutene (BCB) on said passivation layer, wherein an opening in said layer of benzocyclobutene (BCB) is over said contact point.

15. The method of claim 1 further comprising providing a polymer layer on said passivation layer, wherein an opening in said polymer layer is over said contact point.

16. The method of claim 1 further comprising providing a layer of polyimide on said passivation layer, wherein an opening in said layer of polyimide is over said contact point.

17. The method of claim 1 further comprising providing a polymer layer with a thickness between 2 and 150 micrometers on said passivation layer, wherein an opening in said polymer layer is over said contact point.

54. The method of claim 1, wherein before said mounting said discrete passive component over said second metallization structure, said discrete passive component does not join any substrate.

18. A method of forming an integrated circuit chip, comprising:

providing a silicon substrate, a transistor in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, and a passivation layer over said silicon substrate, over said first metallization structure and over said dielectric layer, wherein an opening in said passivation layer is over a contact point of said first metallization structure, and said contact point is at a bottom of said opening in said passivation layer, wherein said passivation layer comprises a nitride;

forming a second metallization structure connected to said contact point through said opening in said passivation layer, wherein said forming said second metallization structure comprises forming a third metal layer, next forming a photoresist layer on said third metal layer, wherein an opening in said photoresist layer exposes a region of said third metal layer, next forming a nickel layer over said region, next removing said photoresist layer, and then removing said third metal layer not under said nickel layer; and

mounting a discrete passive component over said second metallization structure, wherein said discrete passive component is connected to said contact point through said second metallization structure.

19. The method of claim 18, wherein said mounting said discrete passive component comprises mounting a discrete inductor over said second metallization structure.

20. The method of claim 18, wherein said mounting said discrete passive component comprises mounting a discrete capacitor over said second metallization structure.

21. The method of claim 18, after said forming said second metallization structure, further comprising forming a solder on said second metallization structure, followed by said mounting said discrete passive component further to said solder, wherein said discrete passive component is connected to said second metallization structure through said solder.

22. The method of claim 18, after said forming said second metallization structure, further comprising screen printing a solder on said second metallization structure, followed by said mounting said discrete passive component further to said solder, wherein said discrete passive component is connected to said second metallization structure through said solder.

23. The method of claim 18, wherein said forming said third metal layer comprises sputtering a titanium-containing layer.

24. The method of claim 18, wherein said forming said nickel layer comprises an electroplating process.

25. The method of claim 18, wherein said forming said third metal layer comprises sputtering a titanium-tungsten-alloy layer.

26. The method of claim 18, wherein said forming said third metal layer comprises sputtering a chromium-containing layer.

27. The method of claim 18, wherein said forming said third metal layer comprises sputtering a copper layer.

28. The method of claim 18 further comprising said forming said nickel layer with a thickness between 0.1 and 3 micrometers.

29. The method of claim 18 further comprising providing a polymer layer on said passivation layer, wherein an opening in said polymer layer is over said contact point.

30. The method of claim 18 further comprising providing a layer of polyimide on said passivation layer, wherein an opening in said layer of polyimide is over said contact point.

31. The method of claim 18 further comprising providing a polymer layer with a thickness between 2 and 150 micrometers on said passivation layer, wherein an opening in said polymer layer is over said contact point.

46. The method of claim 18, wherein said mounting said discrete passive component comprises mounting a discrete resistor on said solder.

55. The method of claim 18, wherein before said mounting said discrete passive component over said second metallization structure, said discrete passive component does not join any substrate.

32. A method of forming an integrated circuit chip, comprising:

providing a silicon substrate, a transistor in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, and a passivation layer over said silicon substrate, over said first metallization structure and over said dielectric layer, wherein an opening in said passivation layer is over a contact point of said first metallization structure, and said contact point is at a bottom of said opening in said passivation layer, wherein said passivation layer comprises a nitride;

forming a second metallization structure on said contact point and over said passivation layer, wherein said forming said second metallization structure comprises forming a glue layer, next sputtering a seed layer on said glue layer, next forming a photoresist layer on said seed layer, wherein an opening in said photoresist layer exposes a region of said seed layer, next forming a nickel layer over said region, next removing said photoresist layer, and then removing said seed layer and said glue layer not under said nickel layer;

after said forming said second metallization structure, forming a solder on said second metallization structure; and

mounting a discrete passive component on said solder, wherein said discrete passive component is connected to said second metallization structure through said solder.

33. The method of claim 32, wherein said mounting said discrete passive component comprises mounting a discrete inductor on said solder.

34. The method of claim 32, wherein said mounting said discrete passive component comprises mounting a discrete capacitor on said solder.

35. The method of claim 32, wherein said mounting said discrete passive component comprises mounting a discrete resistor on said solder.

36. The method of claim 32, wherein said forming said solder comprises a screen-printing process.

37. The method of claim 32, wherein said forming said glue layer comprises a sputtering process.

38. The method of claim 32, wherein said forming said nickel layer comprises an electroplating process.

39. The method of claim 32, wherein said forming said glue layer comprises sputtering a titanium-containing layer.

40. The method of claim 32, wherein said forming said glue layer comprises sputtering a chromium-containing layer.

41. The method of claim 32, wherein said sputtering said seed layer comprises sputtering a copper layer on said glue layer.

42. The method of claim 32 further comprising said forming said nickel layer with a thickness between 0.1 and 3 micrometers.

43. The method of claim 32 further comprising providing a polymer layer on said passivation layer, wherein an opening in said polymer layer is over said contact point.

44. The method of claim 32 further comprising providing a layer of polyimide on said passivation layer, wherein an opening in said layer of polyimide is over said contact point.

45. The method of claim 32 further comprising providing a polymer layer with a thickness between 2 and 150 micrometers on said passivation layer, wherein an opening in said polymer layer is over said contact point.

56. The method of claim 32, wherein before said mounting said discrete passive component on said solder, said discrete passive component does not join any substrate.

47. A method of forming a circuit component, comprising:

providing a silicon substrate, a transistor in and on said silicon substrate, a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a metal pad over said silicon substrate, a separating layer over said metallization structure and over said dielectric layer, wherein a first opening in said separating layer is over a contact point of said metal pad, and said contact point is at a bottom of said first opening, wherein said separating layer comprises a nitride layer, and a polymer layer on said separating layer, wherein a second opening in said polymer layer is over said contact point;

providing a metal bump on said contact point and on said polymer layer, wherein said metal bump is connected to said contact point through said second opening, wherein providing a bottom portion of said metal bump comprises forming a third metal layer on said contact point and on said polymer layer, next forming a photoresist layer on said third metal layer, wherein a third opening in said photoresist layer exposes a region of said third metal layer, next electroplating a copper layer over said region, next removing said photoresist layer, and then removing said third metal layer not under said copper layer, wherein said metal bump further comprises a top portion made of a solder over said bottom portion; and

providing a discrete passive component over said top portion of said metal bump and over said polymer layer, wherein said discrete passive component is connected to said contact point through said metal bump.

48. The method of claim 47, wherein said providing said bottom portion of said metal bump further comprises forming a nickel layer on said copper layer.

49. The method of claim 47, wherein said discrete passive component comprises a capacitor.

50. The method of claim 47, wherein said providing said bottom portion of said metal bump further comprises said electroplating said copper layer with a thickness between 3 and 20 micrometers.

51. The method of claim 47, wherein said polymer layer has a thickness between 2 and 150 micrometers.

52. The method of claim 47, wherein said providing said bottom portion of said metal bump further comprises forming a nickel layer on said copper layer, followed by said removing said photoresist layer.

53. The method of claim 47, wherein before said providing said discrete passive component over said top portion of said metal bump and over said polymer layer, said discrete passive component does not join any substrate.