Reducing high-frequency signal loss in substrates

• US 8,129,817 B2
• Filed: 12/31/2008
• Issued: 03/06/2012
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jou, Chewn-Pu, Chen, Ho-Hsiang
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US12/347,208
• Publication Number:
  US 20100164069A1
• Time in Patent Office: 1,161 Days
• Field of Search: 257/544, 257/545, 257/547, 257/E29.019
• US Class Current: 257/544
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type. The depletion region includes a first portion directly over the deep well region and a second portion directly under the deep well region. An integrated circuit device is directly over the depletion region.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate of a first conductivity type;

a deep well region of a second conductivity type opposite the first conductivity type in the semiconductor substrate, wherein the deep well region comprises a plurality of fingers, with portions of the semiconductor substrate extending into spaces between the plurality of fingers, and wherein the plurality of fingers is interconnected to form the deep well region;

a depletion region in the semiconductor substrate and adjoining the deep well region, wherein the depletion region comprises portions formed by the plurality of fingers, and wherein the portions of the depletion region are overlapped to form a continuous depletion region;

a voltage source connected to the deep well region, wherein the voltage source is configured to provide a fixed positive voltage to the deep well region; and

an integrated circuit device directly over the depletion region.

2. The integrated circuit structure of claim 1, wherein the deep well region is of n-type, and wherein a portion of the semiconductor substrate directly over the deep well region and a portion of the semiconductor substrate directly under the deep well region are of p-type.

3. The integrated circuit structure of claim 1, wherein the fixed positive voltage is a positive power supply voltage of a core circuit.

4. The integrated circuit structure of claim 1, wherein the fixed positive voltage is a positive power supply voltage of an input/output circuit.

5. The integrated circuit structure of claim 1, wherein the integrated circuit device is a radio frequency (RF) transformer.

6. The integrated circuit structure of claim 5 further comprising a dielectric layer over the semiconductor substrate and spacing the depletion region apart from the RF transformer.

7. The integrated circuit structure of claim 1, wherein the integrated circuit device is a diode.

8. The integrated circuit structure of claim 7, wherein the diode is a junction diode comprising a first well region in the semiconductor substrate, and a second well region in the first well region, wherein the first well region and the second well region are of opposite conductivity types.

9. The integrated circuit structure of claim 7, wherein the diode is a FinFET diode comprising a first fin region over the semiconductor substrate, and a second fin region over the semiconductor substrate and contacting the first fin region, and wherein the first fin region and the second fin region are of opposite conductivity types.

10. The integrated circuit structure of claim 7, wherein the diode is a Schottky diode.

11. The integrated circuit structure of claim 1, wherein the depletion region has an area substantially no less than an area of the integrated circuit device.

12. The integrated circuit structure of claim 1, wherein the deep well region comprises a plurality of deep well fingers parallel to each other.

13. The integrated circuit structure of claim 12, wherein widths of the plurality of deep well fingers are close to a minimum width of a technology for forming the integrated circuit structure.

14. An integrated circuit structure comprising:

a semiconductor substrate of a first conductivity type;

a diode;

a deep well region in the semiconductor substrate and directly under the diode, wherein the deep well region is of a second conductivity type opposite the first conductivity type;

a voltage source connected to the deep well region and configured to provide a fixed positive voltage to the deep well region, wherein the fixed positive voltage is selected from the group consisting of a positive power supply voltage of a core circuit and a positive power supply voltage of an input/output circuit; and

a depletion region comprising a first portion directly over the deep well region and a second portion directly under the deep well region, wherein the first portion spaces the deep well region apart from the diode.

15. The integrated circuit structure of claim 14, wherein the first portion and the second portion of the depletion region are portions of a continuous depletion region substantially enclosing the deep well region.

16. The integrated circuit structure of claim 14, wherein the diode is a junction diode comprising a first well region in the semiconductor substrate, and a second well region in the first well region, wherein the first well region and the second well region are of opposite conductivity types.

17. The integrated circuit structure of claim 14, wherein the depletion region extends to a top surface of the semiconductor substrate, wherein the diode is a FinFET diode comprising a first fin region over the semiconductor substrate, and a second fin region over the semiconductor substrate and contacting the first fin region, and wherein the first fin region and the second fin region are of opposite conductivity types.

18. The integrated circuit structure of claim 14, wherein the diode is a Schottky diode comprising:

a doped semiconductor region in the semiconductor substrate; and

a metal contact plug contacting the doped semiconductor region.

19. The integrated circuit structure of claim 14, wherein the first conductivity type is n-type, the second conductivity type is p-type, and wherein the voltage source is configured to provide a negative voltage.

20. The integrated circuit structure of claim 14, wherein the depletion region has an area substantially no less than an area of the diode.

21. The integrated circuit structure of claim 20, wherein the area of the depletion region is greater than the area of the diode, and wherein the depletion region substantially laterally extends beyond respective edges of the diode in all lateral directions.

22. The integrated circuit structure of claim 14, wherein the deep well region comprises a plurality of deep well fingers, with the depletion region extending to between the plurality of deep well fingers.

23. The integrated circuit structure of claim 14, wherein the deep well region comprises a plurality of deep n-well fingers parallel to each other, and an additional n-well strip interconnecting the plurality of deep n-well fingers.

24. An integrated circuit structure comprising:

a semiconductor substrate of a first conductivity type;

a depletion region in the semiconductor substrate;

a deep well region substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type, and wherein the depletion region comprises a first portion directly over the deep well region and a second portion directly under the deep well region;

a voltage source connected to the deep well region, wherein the voltage source is configured to provide a fixed positive voltage to the deep well region, and wherein the fixed positive voltage is selected from the group consisting of a positive power supply voltage of a core circuit and a positive power supply voltage of an input/output circuit; and

an integrated circuit device directly over the depletion region.