Semiconductor device and method of forming interconnect structure in non-active area of wafer

• US 8,129,845 B2
• Filed: 09/09/2008
• Issued: 03/06/2012
• Est. Priority Date: 09/25/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Jang, TaeHoan, Ku, JaeHun, Bao, XuSheng
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): JEFFERSON, QUOVAUNDA
• Application Number:
  US12/207,324
• Publication Number:
  US 20090079069A1
• Time in Patent Office: 1,274 Days
• Field of Search: 438106-110, 438/113, 438/FOR.369, 438/FOR.379, 438/FOR.384, 438/127, 438/584, 438/612, 438/613, 438/926, 438/FOR.343, 438/FOR.340, 438/FOR.364, 257/620, 257/621, 257/737, 257/773, 257/776, 257/E23.011, 257/E23.126, 257/E21.499, 257/E21.502, 257/E21.503, 257/E21.523, 257/E21.59, 257/E21.705, 257/734, 257/738, 257/772, 257/778, 257/779, 257/781, 257/E23.023, 257/E23.01, 257/E23.141, 257/E23.168, 257/E23.169, 257/E21.508, 257/684, 257/E25.027, 257/E21.512, 257/E21.614
• US Class Current: 257/776
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/1184 involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/14051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/17051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/27 : Manufacturing methods
• CPC Class Codes: H01L 2224/274 : by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/2741 : in liquid form
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48 : of an individual wire connector
• CPC Class Codes: H01L 2224/73104 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor wafer includes a plurality of semiconductor die. Contact pads are formed on an active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. Solder bumps are formed on the contact pads in both the active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. The I/O terminal count of the semiconductor die is increased by forming solder bumps in the non-active area of the wafer. An encapsulant is formed over the solder bumps. The encapsulant provides structural support for the solder bumps formed in the non-active area of the semiconductor wafer. The semiconductor wafer undergoes grinding after forming the encapsulant to expose the solder bumps. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a package substrate with solder paste or socket.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die;

forming contact pads in an active area of the semiconductor die and in a non-active area of the semiconductor wafer between the semiconductor die;

forming conductive bumps on the contact pads in the active area of the semiconductor die and in the non-active area of the semiconductor wafer between the semiconductor die;

forming an encapsulant over the conductive bumps;

singulating the semiconductor wafer to separate the semiconductor die; and

mounting the semiconductor die to a package substrate.

2. The method of claim 1, wherein the encapsulant provides structural support for the conductive bumps formed in the non-active area of the semiconductor wafer between the semiconductor die.

3. The method of claim 1, further including mounting the semiconductor die to the package substrate with solder paste.

4. The method of claim 1, further including:

providing a socket base on the package substrate;

mounting the semiconductor die to the socket base; and

electrically connecting the conductive bumps to electrodes on the socket base.

5. The method of claim 1, further including grinding the semiconductor wafer after forming the encapsulant to expose the conductive bumps.

6. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die;

forming contact pads in a non-active area of the semiconductor wafer between the semiconductor die;

forming an interconnect structure on the contact pads in the non-active area of the semiconductor wafer between the semiconductor die; and

forming an encapsulant over the interconnect structure.

7. The method of claim 6, wherein the interconnect structure includes conductive bumps, conductive posts, or wire bond sites.

8. The method of claim 6, further including forming the interconnect structure in the active area of the semiconductor die.

9. The method of claim 6, further including:

singulating the semiconductor wafer to separate the semiconductor die; and

mounting the semiconductor die to a package substrate.

10. The method of claim 6, wherein the encapsulant provides structural support for the interconnect structure formed in the non-active area of the semiconductor wafer between the semiconductor die.

11. The method of claim 6, further including mounting the semiconductor die to the package substrate with solder paste.

12. The method of claim 6, further including:

providing a socket base on the package substrate;

mounting the semiconductor die to the socket base; and

electrically connecting the interconnect structure to electrodes on the socket base.

13. The method of claim 6, further including grinding the semiconductor wafer after forming the encapsulant to expose the interconnect structure.

14. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die;

forming an interconnect structure in a non-active area of the semiconductor wafer between the semiconductor die; and

forming an encapsulant over the interconnect structure.

15. The method of claim 14, further including:

forming contact pads in the non-active area of the semiconductor wafer between the semiconductor die; and

forming the interconnect structure on the contact pads in the non-active area of the semiconductor wafer between the semiconductor die.

16. The method of claim 14, wherein the interconnect structure includes conductive bumps, conductive posts, or wire bond sites.

17. The method of claim 14, further including:

singulating the semiconductor wafer to separate the semiconductor die; and

mounting the semiconductor die to a package substrate.

18. The method of claim 14, wherein the encapsulant provides structural support for the interconnect structure formed in the non-active area of the semiconductor wafer between the semiconductor die.

19. The method of claim 14, further including mounting the semiconductor die to the package substrate with solder paste.

20. The method of claim 14, further including:

providing a socket base on the package substrate;

mounting the semiconductor die to the socket base; and

electrically connecting the interconnect structure to electrodes on the socket base.

21. The method of claim 14, further including grinding the semiconductor wafer after forming the encapsulant to expose the interconnect structure.

22. A semiconductor device, comprising:

a semiconductor wafer including a plurality of semiconductor die;

an interconnect structure formed in a non-active area of the semiconductor wafer between the semiconductor die; and

an encapsulant formed over the interconnect structure.

23. The semiconductor device of claim 22, further including a plurality of contact pads formed on the non-active area of the semiconductor wafer between the semiconductor die, the interconnect structure being formed on the contact pads in the non-active area of the semiconductor wafer between the semiconductor die.

24. The semiconductor device of claim 22, wherein the interconnect structure includes conductive bumps, conductive posts, or wire bond sites.

25. The semiconductor device of claim 22, wherein the encapsulant provides structural support for the interconnect structure formed in the non-active area of the semiconductor wafer between the semiconductor die.