Method of making semiconductor package with adhering portion

• US 8,129,849 B1
• Filed: 10/28/2009
• Issued: 03/06/2012
• Est. Priority Date: 05/24/2006
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Youn Sang, Kim, Bong Chan, Kim, Yoon Joo
• Primary Examiner(s): Le, Thao
• Assistant Examiner(s): PARKER, ALLEN L
• Application Number:
  US12/589,868
• Time in Patent Office: 860 Days
• Field of Search: 257/787, 257/E21.504, 257/687, 257/723, 257/678
• US Class Current: 257/787
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

Disclosed are a semiconductor package and a method of making the same. In the semiconductor package, a substrate and a semiconductor die are covered with and encapsulated by vertically pressing thermosetting resin having fluidity in a predetermined temperature range and denaturalizing itself in gel. Thus, it is possible to reduce a thickness of the semiconductor package and prevent wire sweeping.

Claims

1. A method of making a semiconductor package comprising:

forming solder masks on a substrate which has a plurality of conductive patterns formed on upper and lower surfaces of the substrate, in such a manner that the solder masks are formed on the conductive patterns except for a region of the conductive patterns in which bond fingers and ball lands are formed;

attaching a semiconductor die to the upper portion of the substrate using adhesive;

bonding the semiconductor die to the conductive patterns electrically by means of conductive wires;

attaching an adhering portion, made of thermosetting resin having fluidity in a predetermined temperature range, to a supporting portion for supporting the adhering portion, to form an encapsulant, the supporting portion having;

a lower surface with a total area identical with a total area of an upper surface of the adhering portion;

an upper surface with a total area identical with the total area of the upper surface of the adhering portion; and

sides directly extending between the upper surface of the supporting portion and the lower surface of the supporting portion;

performing a first heating process for heating the adhering portion in the fluidity state;

pressing the encapsulant vertically downwards so that the adhering portion covers the semiconductor die and the conductive wires placed on the upper surface of the substrate, the supporting portion having enough hardness to maintain flatness of the encapsulant;

performing a second heating process for heating the adhering portion at a predetermined temperature so as to cure the adhering portion after the pressing; and

fusion-welding solder balls to the ball lands;

wherein the supporting portion is selected from the group consisting of polyimide and epoxy.

2. The method of making the semiconductor package as claimed in claim 1, further comprising separating the supporting portion from the adhering portion.

3. The method of making the semiconductor package as claimed in claim 2, further comprising coloring the adhering portion.

4. The method of making the semiconductor package as claimed in claim 1, wherein in the bonding, the wires are bonded to the bond fingers of the substrate in a ball bonding manner and to the die pads of the semiconductor die in a stitch bonding manner.

5. The method of making the semiconductor package as claimed in claim 1, wherein the first heating process is performed at a temperature of 50°

C. to 200°

C.

6. The method of making the semiconductor package as claimed in claim 1, wherein the second heating process is performed at a temperature of 50°

C. to 200°

C. for a half hour to six hours.

7. The method as claimed in claim 1 wherein the semiconductor package includes the supporting portion.

8. The method as claimed in claim 1 wherein the supporting portion has a uniform thickness between the upper surface of the supporting portion and the lower surface of the supporting portion.

9. The method as claimed in claim 1 wherein the sides of the supporting portion are coplanar with sides of the adhering portion.

10. A method of making a semiconductor package comprising:

attaching a semiconductor die to an upper surface of a substrate using adhesive;

electrically connecting die pads of the semiconductor die to conductive patterns of the substrate with conductive wires;

supporting an adhering portion of an encapsulant with a supporting portion of the encapsulant, the supporting portion having;

a lower surface with a total area identical with a total area of an upper surface of the adhering portion;

an upper surface with a total area identical with the total area of the upper surface of the adhering portion; and

sides directly extending between the upper surface of the supporting portion and the lower surface of the supporting portion;

heating the adhering portion into a fluidity state;

pressing the adhering portion vertically downwards in the fluidity state to cover the semiconductor die and the conductive wires, the supporting portion having enough hardness to maintain flatness of the encapsulant; and

curing the adhering portion after the pressing;

wherein the supporting portion is selected from the group consisting of polyimide and epoxy.

11. The method of making the semiconductor package as claimed in claim 10, further comprising coloring the supporting portion to have a color other than black.

12. The method of making the semiconductor package as claimed in claim 10, further comprising separating the supporting portion from the adhering portion.

13. The method of making the semiconductor package as claimed in claim 12, further comprising coloring the adhering portion to have a color other than black.

14. A method comprising:

providing a plurality of substrates connected together;

attaching semiconductor dies to upper surfaces of the substrates;

forming conductive wires to electrically connect die pads of the semiconductor dies to conductive patterns of the substrates;

heating an adhering portion of an encapsulant,

wherein the encapsulant further comprises a supporting portion having;

a lower surface with a total area identical with a total area of an upper surface of the adhering portion;

an upper surface with a total area identical with the total area of the upper surface of the adhering portion; and

sides directly extending between the upper surface of the supporting portion and the lower surface of the supporting portion; and

pressing the adhering portion vertically downwards to simultaneously cover the semiconductor dies and the conductive wires;

wherein the supporting portion is selected from the group consisting of polyimide and epoxy.

15. The method as claimed in claim 14 further comprising curing the adhering portion.

16. The method as claimed in claim 15 further comprising singulating the encapsulant and substrates to form a plurality of semiconductor packages.

17. The method as claimed in claim 16 wherein the singulating comprises sawing.

18. The method as claimed in claim 14 wherein the supporting portion supports the adhering portion.

19. The method as claimed in claim 14, further comprising separating the supporting portion from the adhering portion.

20. The method as claimed in claim 14 wherein the adhering portion is made of thermosetting resin having fluidity in a predetermined temperature range.

21. The method as claimed in claim 14 further comprising forming solder balls on ball lands of the substrates.