Post amplifier with selectable gain

• US 8,130,035 B2
• Filed: 06/12/2009
• Issued: 03/06/2012
• Est. Priority Date: 09/15/2003
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Weigandt, Todd C., Gilbert, Barrie
• Primary Examiner(s): Choe, Henry
• Application Number:
  US12/483,786
• Publication Number:
  US 20090302948A1
• Time in Patent Office: 998 Days
• Field of Search: 330/254, 330/252, 330/257, 330/260, 330/261
• US Class Current: 330/254
• CPC Class Codes: G01S 7/52033 Gain control of receivers for seismic signals G01V1/245
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2200/211 the input of an amplifier can be attenuated by a continuously controlled transistor attenuator
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45288 Differential amplifier with circuit arrangements to enhance the transconductance
• CPC Class Codes: H03F 2203/45366 the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45506 the CSC comprising only one switch
• CPC Class Codes: H03F 2203/45521 the FBC comprising op amp stages, e.g. cascaded stages of the dif amp and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45552 the IC comprising clamping means, e.g. diodes
• CPC Class Codes: H03F 2203/45684 the LC comprising one or more buffers or driving stages not being of the emitter respectively source follower type, between the output of the dif amp and the output stage
• CPC Class Codes: H03F 2203/45686 the LC comprising one or more potentiometers, which are not shunting potentiometers
• CPC Class Codes: H03F 3/45094 Folded cascode stages
• CPC Class Codes: H03F 3/45098 PI types H03F3/45125, H03F3/45152 take precedence
• CPC Class Codes: H03F 3/45278 using BiFET transistors as the active amplifying circuit
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45484 in differential amplifiers with bipolar transistors as the active amplifying circuit H03F3/4578 takes precedence
• CPC Class Codes: H03F 3/45928 : using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0088 : using discontinuously variable devices, e.g. switch-operated

Abstract

A selectable gain amplifier includes two or more selectable gain stages, each gain stage having a first input coupled to receive an input signal, a second input, and an output. The amplifier further includes and two or more feedback paths coupled between the outputs and the second inputs of the selectable gain stages.

Claims

1. A selectable gain amplifier comprising:

two or more selectable gain stages, each gain stage having a first input coupled to receive an input signal, a second input, and an output; and

two or more feedback paths coupled between the outputs and the second inputs of the selectable gain stages;

where each selectable gain stage includes a transconductance (gm) cell arranged to be selectively enabled by applying a bias current or disabled by removing the bias current to the gm cell.

2. The amplifier of claim 1 where the amplifier is arranged to provide substantially constant bandwidth regardless of which gain stage is selected.

3. The amplifier of claim 1 where the amplifier is arranged for substantially constant input referred noise regardless of which gain stage is selected.

4. The amplifier of claim 1 further comprising an integrator coupled between the outputs of the gain stages and the feedback paths.

5. The amplifier of claim 4 where the gm cells are arranged to operate at different transconductances when selected.

6. The amplifier of claim 5 where the feedback paths comprise resistive dividers.

7. The amplifier of claim 5 further comprising a cascode stage coupled between the outputs of the gain stages and the integrator.

8. The amplifier of claim 5 further comprising an output stage coupled between the integrator and the feedback paths.

9. The amplifier of claim 8 where the output stage comprises a self-limiting circuit.

10. The amplifier of claim 4 where:

the gm cells are arranged to operate at different transconductances when selected;

the integrator comprises a capacitor;

the feedback paths comprise resistive dividers;

the first inputs of the gm cells are coupled together to receive the input signal;

the outputs of the gm cells are coupled in parallel; and

the second input of each gm cell is coupled to one of the resistive dividers.

11. The amplifier of claim 10 further comprising a folded cascode stage coupled between the outputs of the gm cells and the capacitor.

12. The amplifier of claim 11 further comprising a push-pull output stage coupled between the capacitor and the resistive dividers.

21. The amplifier of claim 7 where the cascode stage is arranged with selectable bias to coordinate with the selectable gain stages.

22. The amplifier of claim 21 where the amplifier is arranged for matching of amplifier dynamics at different gain settings.

23. The amplifier of claim 21 where the amplifier is arranged for substantially constant input referred noise regardless of which gain stage is selected.

24. The amplifier of claim 21 where the amplifier is arranged to reduce net input referred noise at the each gain setting, while maintaining similar amplifier dynamics between different gain settings.

25. The amplifier of claim 21 further comprising:

one or more first bias resistors to bias the cascode stage when a first one of the gain stages is selected; and

one or more second bias resistors to bias the cascode stage when a second one of the gain stages is selected.

26. The amplifier of claim 25 further comprising one or more saturating switches to control the one or more second bias resistors.

27. The amplifier of claim 9 where the self-limiting circuit is arranged to provide a gradual clamping effect as the input to the amplifier increases.

28. The amplifier of claim 27 where the clamping becomes sharper as the input to the amplifier continues to increase.

29. The amplifier of claim 28 where the self-limiting circuit includes a clamp transistor having a first terminal connected to an input node of the output stage, and a second terminal connected to a clamp voltage reference, where the clamp transistor is arranged to conduct as a diode between the first and second terminals as the input to the amplifier increases.

30. The amplifier of claim 29 where the clamp transistor includes a third terminal arranged to divert current from the input node of the output stage as the input to the amplifier continues to increase.

31. The amplifier of claim 30 where the clamp transistor is arranged to use negative feedback to reduce the amount of current driven into the input node of the output stage.

32. The amplifier of claim 27 where the self-limiting circuit is arranged to provide bi-directional clamping.

33. The amplifier of claim 1 where the two or more selectable gain stages are arranged to be selected in response to one or more signals that are separate from the input signal.

13. A selectable gain amplifier comprising:

two or more first selectable gain stages, each first gain stage having a first input coupled to receive a first side of a differential input signal, a second input, and an output;

two or more second selectable gain stages, each second gain stage having a first input coupled to receive a second side of the differential input signal, a second input, and an output; and

two or more differential feedback paths coupled between the outputs and the second inputs of the first and second selectable gain stages;

where each of the first selectable gain stages includes a first transconductance (gm) cell arranged to be selectively enabled by applying a bias current or disabled by removing the bias current to the gm cell; and

where each of the second selectable gain stages includes a second transconductance (gm) cell arranged to be selectively enabled by applying a bias current or disabled by removing the bias current to the gm cell.

14. The amplifier of claim 13 where the amplifier is arranged to provide substantially constant bandwidth regardless of which of the first and second gain stages are selected.

15. The amplifier of claim 13 where the amplifier is arranged for substantially constant input referred noise regardless of which of the first and second gain stages are selected.

16. The amplifier of claim 13 further comprising:

a first integrator coupled between the outputs of the first selectable gain stages and the differential feedback paths; and

a second integrator coupled between the outputs of the second selectable gain stages and the differential feedback paths.

17. The amplifier of claim 16 where:

the first and second gm cells are arranged to operate at different transconductances when selected;

the first and second integrators comprise first and second capacitors;

the differential feedback paths comprise resistive dividers;

the first inputs of the first gm cells are coupled together to receive the first side of the differential input signal;

the first inputs of the second gm cells are coupled together to receive the second side of the differential input signal;

the outputs of the first gm cells are coupled in parallel;

the outputs of the second gm cells are coupled in parallel;

the second input of each first gm cell is coupled to a first side of one of the feedback paths; and

the second input of each second gm cell is coupled to a second side of one of the feedback paths.

18. The amplifier of claim 17 further comprising:

a first folded cascode stage coupled between the outputs of the first gm cells and the first capacitor; and

a second folded cascode stage coupled between the outputs of the second gm cells and the second capacitor.

19. A selectable gain amplifier comprising:

a first gm cell having a first input coupled to receive a first input signal;

a first current source arranged to selectively apply a first bias current to the first gm cell, thereby enabling the first gm cell when the first bias current is applied to the first gm cell and disabling the first gm cell when the first bias current is removed from the first gm cell;

a second gm cell having a first input coupled to receive the first input signal;

a second current source arranged to selectively apply a second bias current to the second gm cell, thereby enabling the second gm cell when the second bias current is applied to the second gm cell and disabling the second gm cell when the second bias current is removed from the second gm cell;

a capacitor arranged to integrate output signals from the first and second gm cells;

a first voltage divider coupled between the capacitor and a second input of the first gm cell; and

a second voltage divider coupled between the capacitor and a second input of the second gm cell.

20. The amplifier of claim 19 further comprising:

a pair of resistors coupled to the outputs of the first and second gm;

a pair of cascode transistors and a current minor coupled between the pair of resistors and the capacitor to generate a current to be integrated by the capacitor; and

an output stage coupled between the capacitor and the voltage dividers.