Flexible word-line pulsing for STT-MRAM

• US 8,130,535 B2
• Filed: 09/01/2009
• Issued: 03/06/2012
• Est. Priority Date: 09/01/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Rao, Hari M., Yoon, Sei Seung, Sani, Medhi, Lee, Seung Duk, Cho, Sung
• Primary Examiner(s): Lam, David
• Application Number:
  US12/551,874
• Publication Number:
  US 20110051502A1
• Time in Patent Office: 917 Days
• Field of Search: 365/158, 365/194, 365/189.05, 365/233.11, 365/201, 327/291, 327/156, 327/158
• US Class Current: 365/158
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal having a rising edge triggered by a rising edge of the first clock signal and a falling edge triggered by a rising edge of the second clock signal is output. The output signal is provided to circuitry on the chip, such as a magnetoresistive junction (MTJ) cell of a spin torque transfer magnetic random access memory (STT-MRAM).

Claims

1. A method for generating a signal having a variable pulse width on a semiconductor device, comprising:

receiving a first clock signal on the semiconductor device;

receiving a second clock signal on the semiconductor device having a predetermined delay relative to the first clock signal;

outputting a final signal having a rising edge triggered by the first clock signal and a falling edge triggered by the second clock signal; and

providing the final output signal to circuitry on the semiconductor device.

2. The method of claim 1, in which the outputting comprises outputting the final signal with the rising edge triggered by a rising edge of the first clock signal and the falling edge triggered by a rising edge of the second clock signal.

3. The method of claim 1, further comprising:

providing the final signal to at least one transistor gate on the semiconductor device.

4. The method of claim 1, further comprising:

setting the variable delay from less than 1 ns to approximately 0.9 ms.

5. The method of claim 1, further comprising:

receiving a global reset signal at a first latch, a second latch, and a combinational logic circuit;

receiving at the first latch the first clock signal and a first clock enable signal; and

receiving at the second latch the second clock signal and a second clock enable signal.

6. The method of claim 5, further comprising:

inputting to the combinational logic circuit an output of the second latch;

inputting the output of the combinational logic circuit to a reset input of a set-reset latch; and

outputting from the set-reset latch a pulse signal on the basis of the global reset signal, the first clock signal, the first clock enable signal, the second clock signal, and the second clock enable signal.

7. The method of claim 1, wherein the semiconductor device is applied in an electronic device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the semiconductor device is integrated.

8. A method for generating a signal having a variable pulse width on a semiconductor device, comprising:

receiving a first clock signal on the semiconductor device;

receiving a second clock signal on the semiconductor device having a variable delay relative to the first clock signal;

outputting a final signal having a rising edge triggered by the first clock signal and a falling edge triggered by the second clock signal; and

providing the final output signal to circuitry on the semiconductor device,

wherein the outputting comprises outputting the final signal with the rising edge triggered by a rising edge of the first clock signal and the falling edge triggered by a rising edge of the second clock signal, and further including;

setting a set-reset latch circuit on a basis of the rising edge of the first clock signal;

resetting the set-reset latch circuit on a basis of the rising edge of the second clock signal; and

outputting from the set-reset latch circuit a pulse signal having a pulse width determined on the basis of the setting and resetting of the latch circuit.

9. The method of claim 8, further comprising:

receiving at a multiplexer the pulse signal from the set-reset latch circuit, a third clock signal and a bypass signal; and

outputting either the third clock signal or the pulse signal, as a word line signal, on the basis of the bypass signal.

10. The method of claim 9, further comprising:

receiving the word line signal from the multiplexer at a first input to a combinational logic circuit;

receiving a global word line signal at a second input of the combinational logic circuit; and

outputting the final signal from the combinational logic circuit on the basis of the global word line signal and the word line signal.

11. The method of claim 9, further comprising:

setting the third clock signal to have a pulse width of any duration in time length.

12. A method for generating a signal having a variable pulse width on a semiconductor device, comprising:

receiving a first clock signal on the semiconductor device;

receiving a second clock signal on the semiconductor device having a variable delay relative to the first clock signal;

outputting a final signal having a rising edge triggered by the first clock signal and a falling edge triggered by the second clock signal;

providing the final output signal to circuitry on the semiconductor device;

receiving a global reset signal at the semiconductor device; and

outputting a null signal to circuitry on the semiconductor device on the basis of the global reset signal to enable reading and writing a polarization state to an STT-MRAM cell.

13. An on-chip variable pulse width signal generating circuit comprising:

a first on-chip latch configured to receive a first clock signal;

a second on-chip latch configured to receive a second clock signal delayed from the first clock signal by a predetermined amount; and

an on-chip set-reset latch configured to receive a signal output from the first latch and a signal output from the second latch, and further configured to output a pulse of time duration based on a delay of the signal from the second latch relative to the signal from the first latch.

14. The signal generating circuit of claim 13, in which the first on-chip latch and the second on-chip latch are phase 2 (Ø

2) latches.

15. The signal generating circuit of claim 14, in which the circuit is incorporated in a device selected from the group consisting of a mobile phone, personal data assistant (PDA), navigation device, fixed location data unit, set-top box, music player, video player, entertainment unit, and computer.

16. The signal generating circuit of claim 13, in which the circuit is integrated into a semiconductor die.

17. An on-chip variable pulse width signal generating circuit comprising:

a first on-chip latch configured to receive a first clock signal;

a second on-chip latch configured to receive a second clock signal delayed from the first clock signal by a variable amount; and

an on-chip set-reset latch configured to receive a signal output from the first latch and a signal output from the second latch, and further configured to output a pulse of time duration based on a delay of the signal from the second latch relative to the si nal from the first latch,

wherein,

the first on-chip latch is configured to receive a first clock enable signal and a global reset signal and to output a first signal on the basis of the received first clock signal, first clock enable signal and the global reset signal; and

the second on-chip latch is configured to receive a second clock enable signal and a global reset signal, and to output a second signal on the basis of the received second clock signal, second clock enable signal, and the global reset signal.

18. The signal generating circuit of claim 17, further comprising:

a combinational logic circuit configured to receive the global reset signal and the second signal from the second on-chip latch, wherein the logic circuit is further configured to output a reset signal on the basis of the received global reset signal and the reset signal from the second on-chip latch.

19. The signal generating circuit of claim 18, further comprising:

a multiplexer configured to receive the output pulse from the set-reset latch, a bypass signal, and a third clock signal, and further configured to output either the output pulse from the set-reset latch or the third clock signal based on a level of the bypass signal.

20. The signal generating circuit of claim 19, further comprising:

a second combinational logic circuit configured to receive a global word line signal and the output from the multiplexer, and further configured to output a signal corresponding to the output of the multiplexer on the basis of the global word line signal.

21. An on-chip variable pulse width signal generating circuit for testing a spin-torque-transfer (STT) magnetic tunnel junction (MTJ) memory cell comprising:

a first on-chip latch configured to receive a first clock signal;

a second on-chip latch configured to receive a second clock signal delayed from the first clock signal by a variable amount;

an on-chip set-reset latch configured to receive a signal output from the first latch and a signal corresponding to an output from the second latch, and further configured to output a pulse of time duration based on the delay of the second clock signal relative to the signal from the first clock signal; and

an STT-MTJ memory cell configured to receive a final signal based on the output pulse from the set-reset latch, the STT-MTJ memory cell further comprising;

a bit line adapted to receive a bit line voltage;

an MTJ comprising a free magnetic layer coupled to the bit line and a fixed magnetic layer coupled to a drain of a transistor;

a source of the transistor coupled to a source line, the source line adapted to receive a source line voltage; and

a gate of the transistor adapted to receive a signal corresponding to the output pulse of the set-reset latch.

22. The signal generating circuit of claim 21, in which the circuit is integrated into a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital, assistant (PDA), fixed location data unit, and a computer.

23. A method for generating a signal having a variable pulse width on a semiconductor chip, comprising the steps of:

receiving a first clock signal on the chip;

receiving a second clock signal on the IC chip having a predetermined delay relative to the first clock signal;

outputting a final signal having a rising edge triggered by the first clock signal and a falling edge triggered by the second clock signal; and

providing the final output signal to circuitry on the chip.

24. The method of claim 23, wherein the semiconductor chip is applied in an electronic device, selected from a group consisting of a sot top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the semiconductor chip is integrated.

25. An on-chip variable pulse width signal generating circuit comprising:

a first on-chip means for receiving a first clock signal;

a second on-chip means for receiving a second clock signal delayed from the first clock signal by a predetermined amount; and

a third on-chip means for receiving a signal output from the first receiving means and a signal output from the second receiving means, and for outputting a pulse of time duration based on a delay of the signal received by the second receiving means relative to the signal received by the first receiving means.

26. The signal generating circuit of claim 25, in which the circuit is integrated into a semiconductor die.

27. The signal generating circuit of claim 25, in which the circuit is integrated into a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.