Multi-rank partial width memory modules

• US 8,130,560 B1
• Filed: 11/13/2007
• Issued: 03/06/2012
• Est. Priority Date: 11/13/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Smith, Michael John Sebastian
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US11/939,432
• Time in Patent Office: 1,575 Days
• Field of Search: 365/189.03
• US Class Current: 365/189.03
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A system is provided for multi-rank, partial-width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number of data pins that is less than a second number of data pins of the memory bus.

Claims

1. An apparatus, comprising:

a memory controller;

a memory module including a plurality of ranks of memory circuits, wherein the memory module has a data bus width of a first number of first data pins;

a memory bus including a second number of second data pins, wherein the first number of first data pins are fewer than the second number of second data pins, the first number of first data pins are coupled to a subset of the second number of second data pins, and the memory bus is coupled between the memory controller and the memory module; and

at least one buffer chip that is coupled between the memory circuits and the memory bus, wherein the at least one buffer chip is configured to transform data signals of the memory bus.

2. The apparatus of claim 1, wherein the memory circuits of at least one of the ranks include physical dynamic random access memory (DRAM) circuits.

3. The apparatus of claim 1, wherein the at least one buffer chip is configured to transform the data signals from a first data rate to a second data rate that is two times the first data rate.

4. The apparatus of claim 3, wherein the at least one buffer chip is configured to transform data in the data signals from a first data width to a second data width that is half of the first data width.

5. The apparatus of claim 1, wherein the memory module includes a dual inline memory module (DIMM).

6. The apparatus of claim 5, wherein the dual inline memory module is a registered dual inline memory module (R-DIMM).

7. The apparatus of claim 1, wherein the memory module includes at least four ranks of memory circuits.

8. The apparatus of claim 1, wherein the memory module includes at least six ranks of memory circuits.

9. The apparatus of claim 1, wherein the first number is half of the second number.

10. The apparatus of claim 1, wherein the first number is one-third of the second number.

11. The apparatus of claim 1, wherein the memory module is connected to a proper subset of data transmission lines associated with the memory bus.

12. The apparatus of claim 1, wherein the at least one buffer chip is on the memory module.

13. The apparatus of claim 1, wherein the at least one buffer chip is on a motherboard.

14. The apparatus of claim 1, wherein the at least one buffer chip is configured to transform the data signals from a first data rate to a second data rate.

15. The apparatus of claim 1, wherein the at least one buffer chip is configured to transform the data signals from a first data width to a second data width.

16. The apparatus of claim 1, wherein the at least one buffer chip is configured to reduce a loading of the memory circuits on the memory bus.

17. The apparatus of claim 1, wherein the at least one buffer chip is configured to emulate memory circuits to appear to the memory controller as higher capacity virtual memory circuits with at least one aspect that is different from that of the memory circuits.

18. The apparatus of claim 17, wherein the at least one aspect includes at least one of a number, a signal, a memory capacity, a timing, a latency, a design parameter, a logical interface, a control system, a property, and a behavior.

19. The apparatus of claim 18, wherein the behavior includes a power behavior.

20. The apparatus of claim 1, wherein the memory module corresponds to a part of the plurality of ranks of memory circuits as the ranks appear to the memory bus.

21. The apparatus of claim 1, wherein the memory module corresponds to one or more complete ranks of the memory circuits as the ranks appear to the memory bus.

22. The apparatus of claim 1, further comprising:

another memory module including a plurality of ranks of memory circuits, wherein the other memory module has a data bus width of a third number of data pins, the third number of data pins being fewer than the second number of data pins;

wherein the memory bus is coupled between the memory controller and the memory circuits of the memory modules.

23. The apparatus of claim 22, wherein a sum of the first number of data pins and the third number of data pins equals the second number of data pins.

24. The apparatus of claim 23, wherein the first number of data pins equals the third number of data pins.

25. An apparatus, comprising:

a memory controller;

a memory module including a plurality of ranks of memory circuits, wherein the memory module has a data bus width of a first number of first data pins;

a memory bus including a second number of second data pins, wherein the first number of first data pins are fewer than the second number of second data pins, the first number of first data pins are coupled to a subset of the second number of second data pins, and the memory bus is coupled between the memory controller and the memory module; and

at least one buffer chip coupled between the memory circuits and the memory bus;

wherein the at least one buffer chip is configured to emulate at least one of the memory circuits to appear different to the memory controller in at least one aspect from the at least one of the memory circuits.

26. The apparatus of claim 25, wherein the at least one aspect includes at least one of a memory capacity, a timing, a latency, and a power behavior.

27. An apparatus, comprising:

a memory controller;

a memory module including a plurality of ranks of memory circuits, wherein the memory module has a data bus width of a first number of first data pins;

a memory bus including a second number of second data pins, wherein the first number of first data pins are fewer than the second number of second data pins, the first number of first data pins are coupled to a subset of the second number of second data pins, and the memory bus is coupled between the memory controller and the memory module; and

at least one buffer chip that is coupled between the memory circuits and the memory bus;

wherein the at least one buffer chip is configured to emulate at least one of the memory circuits to appear to the memory controller as a higher capacity virtual dynamic random access memory (DRAM) circuit.

28. An apparatus, comprising:

a memory controller;

a memory module including a plurality of ranks of memory circuits, wherein the memory module has a data bus width of a first number of first data pins;

a memory bus including a second number of second data pins, wherein the first number of first data pins are fewer than the second number of second data pins, the first number of first data pins are coupled to a subset of the second number of second data pins, and the memory bus is coupled between the memory controller and the memory module; and

at least one buffer chip that is coupled between the memory circuits and the memory bus;

wherein each data pin of the memory module is coupled to a single pin of the at least one buffer chip.

29. The apparatus of claim 28, wherein the coupling of the memory module to the at least one buffer chip is configured to reduce loading of the ranks of memory circuits.

30. A sub-system, comprising:

a memory module including a plurality of ranks of memory circuits, wherein the memory module has a data bus width of a first number of first data pins, the memory module is configured to be coupled to a memory bus, the memory bus including a second number of second data pins, wherein the first number of first data pins are fewer than the second number of second data pins, and the first number of first data pins are coupled to a subset of the second number of second data pins;

wherein the memory module further includes at least one buffer chip that is coupled between the memory circuits and the memory bus, and the at least one buffer chip is configured to transform data signals of the memory bus.