Error detection on programmable logic resources

• US 8,130,574 B2
• Filed: 02/10/2011
• Issued: 03/06/2012
• Est. Priority Date: 10/11/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ngo, Ninh D., Lee, Andy L., Veenstra, Kerry
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US13/024,666
• Publication Number:
  US 20110138240A1
• Time in Patent Office: 390 Days
• Field of Search: 365/201, 365/189.07, 714/725, 714/766
• US Class Current: 365/201
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Claims

1. A method for detecting errors in configuration data on a logic device, the method comprising:

selecting, based on a control signal, configuration data stored on the logic device or an expected value as a selected value for receipt by check circuitry;

computing, using the check circuitry, a signature by applying a mathematical function to the selected value received by the check circuitry; and

analyzing, when the expected value is selected, the signature to determine whether the configuration data includes an error.

2. The method of claim 1, wherein the selecting comprises:

receiving at a first input of selection circuitry the configuration data; and

receiving at a second input of the selection circuitry the expected value;

providing as an output of the selection circuitry the selected value corresponding to the first input or the second input.

3. The method of claim 1, wherein the mathematical function comprises a polynomial checksum computation implemented on the logic device as an XOR tree.

4. The method of claim 1 further comprising:

receiving, using selection circuitry, the expected value and the signature; and

selecting, using the selection circuitry, the expected value or the signature for output to shifting circuitry.

5. The method of claim 1, wherein:

when the mathematical function is applied only to the configuration data, the signature is the expected value; and

when the mathematical function is applied to the expected value after being applied to the configuration data, the signature is a zero value.

6. The method of claim 1 further comprising:

storing the configuration data in a memory external to the logic device;

computing the expected value, using a device external to the logic device, by applying the mathematical function to the configuration data stored in the memory external to the logic device.

7. The method of claim 6, wherein the computed expected value is combined with the configuration data before the configuration data is programmed onto the logic device.

8. The method of claim 1, wherein the expected value is computed on the logic device from the configuration data while the configuration data is being programmed onto the logic device.

9. The method of claim 1, wherein:

the expected value is selected after the configuration data is selected and after the mathematical function is applied to every bit of the configuration data; and

the signature is analyzed after the mathematical function is applied to the expected value and the configuration data.

10. A system for detecting errors in configuration data on a logic device, the system comprising:

a memory on the logic device in which configuration data having a plurality of portions and an expected value are stored; and

control circuitry configured to;

for each of the plurality of portions of the configuration data;

retrieve the portion of the configuration data from the memory; and

process the portion with a mathematical function to update a signature value;

after the signature value is updated based on each portion of the plurality of portions of the configuration data, update the signature value by processing the stored expected value with the mathematical function; and

determine whether the configuration data includes an error based on the updated signature value.

11. The system of claim 10, wherein the portions of the configuration data are processed while the configuration data is being programmed onto the logic device.

12. The system of claim 10, wherein the mathematical function comprises a polynomial checksum computation implemented on the logic device as an XOR tree.

13. The system of claim 10, wherein:

when the mathematical function is applied only to the configuration data, the expected value is output; and

when the mathematical function is applied to the configuration data combined with the expected value, a zero value is output.

14. The system of claim 10, wherein the control circuitry is configured to determine that the configuration data includes an error when the signature value corresponds to a predetermined number.

15. The system of claim 10, wherein the signature value represents a type of error in the configuration data.

16. A non-transitory computer readable medium for detecting errors in configuration data on a logic device, the non-transitory computer readable medium comprising computer program code recorded thereon for:

selecting, based on a control signal, configuration data stored on the logic device or an expected value as a selected value for receipt by check circuitry;

computing, using the check circuitry, a signature by applying a mathematical function to the selected value received by the check circuitry; and

analyzing, when the expected value is selected, the signature to determine whether the configuration data includes an error.

17. The non-transitory computer readable medium of claim 16, wherein the mathematical function comprises a polynomial checksum computation implemented on the logic device as an XOR tree.

18. The non-transitory computer readable medium of claim 17, further comprising machine program logic for:

receiving, using selection circuitry, the expected value and the computed signature; and

selecting, using the selection circuitry, the expected value or the computed signature for output to shifting circuitry.

19. The non-transitory computer readable medium of claim 16, wherein:

when the mathematical function is applied only to the configuration data, the signature is the expected value; and

when the mathematical function is applied to the expected value after being applied to the configuration data, the signature is a zero value.

20. The non-transitory computer readable medium of claim 16, wherein the expected value is computed on the logic device from the configuration data while the configuration data is being programmed onto the logic device.