Integrated circuit having radio receiver and methods for use therewith

• US 8,130,871 B2
• Filed: 01/09/2006
• Issued: 03/06/2012
• Est. Priority Date: 01/09/2006
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: May, Michael R., Lowe, Erich
• Primary Examiner(s): Tran, Khanh C
• Assistant Examiner(s): HUGHES, EBONI N
• Application Number:
  US11/328,830
• Publication Number:
  US 20070160167A1
• Time in Patent Office: 2,248 Days
• Field of Search: 375/219, 375/316, 375/344, 375/340, 375/349, 375/322, 375/326, 370/100.1, 341/117, 341/143, 341/155, 327/291
• US Class Current: 375/316
• CPC Class Codes: H03D 5/00 Circuits for demodulating amplitude-modulated or angle-modulated oscillations at will H03D9/00, H03D11/00 take precedence
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes

Abstract

An integrated circuit includes a radio receiver for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies. The radio receiver converts a selected one of the plurality of channel signals into a demodulated signal. An interface clock generator generates a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals. The first interface clock frequency, and integer multiples of the first clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A driver module drives a device interface with a device based on the first interface clock.

Claims

1. An integrated circuit comprising:

a radio receiver module to receive a radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and to convert a selected one of the plurality of channel signals into an output signal;

a channel selector module to produce a control signal;

a programmable decimation filter, responsive to the control signal, to down-sample the output signal to produce a down-sampled digital signal at a frequency that is a non-integer multiple of a carrier frequency of the selected one of the plurality of channel signals;

an interface clock generator, responsive to the control signal, to generate a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals wherein the first interface clock frequency, and integer multiples of the first interface clock frequency, are non-integer multiples of the carrier frequency of the selected one of the plurality of channel signals; and

a driver module, operably coupled to the interface clock generator, to drive a device interface to couple a device to the radio receiver module based on the first interface clock;

wherein the device interface is a bidirectional interface that is configured to exchange control data between the radio receiver module and the device.

2. The integrated circuit of claim 1 wherein the driver module produces a device interface signal that is clocked at the first interface clock frequency.

3. The integrated circuit of claim 2 wherein the device interface signal includes an audio channel signal.

4. The integrated circuit of claim 1 wherein the driver module receives a device interface signal that is sampled at the first interface clock frequency.

5. The integrated circuit of claim 4 wherein the device interface signal includes control data.

6. The integrated circuit of claim 1 wherein the interface clock generator includes:

a controller module to produce a first divisor that varies based on the carrier frequency of the selected one of the plurality of channel signals; and

a first programmable divider module, operably coupled to the controller module, to produce the first interface clock by dividing a reference oscillation by the first divisor.

7. The integrated circuit of claim 6 wherein the first programmable divider module includes a fractional divider.

8. The integrated circuit of claim 6 wherein the controller module further produces a second divisor that varies based on the carrier frequency of the selected one of the plurality of channel signals and wherein the interface clock generator further includes a second programmable divider module, operably coupled to the controller module, to produce a second interface clock by dividing the reference oscillation by the second divisor.

9. The integrated circuit of claim 1 wherein the interface clock generator includes:

a first divider module to produce the first interface clock by dividing a local oscillation signal by a first divisor.

10. The integrated circuit of claim 9 wherein the first divider module includes a fractional divider.

11. The integrated circuit of claim 9 wherein the interface clock generator includes:

a second divider module to produce a second interface clock by dividing the local oscillation signal by a second divisor.

12. The integrated circuit of claim 1 wherein the device interface is an integrated circuit device.

13. The integrated circuit of claim 1 wherein the first interface clock frequency is less than the carrier frequency of the selected one of the plurality of channel signals.

14. The integrated circuit of claim 1 wherein the received radio signal is one of a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, and a broadcast cable signal.

15. The integrated circuit of claim 1 wherein the radio receiver module includes an in-phase signal path and a quadrature-phase signal path.

16. A method comprising:

receiving, at a radio receiver module, a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies;

selecting a channel signal from the plurality of channel signals and producing a control signal based on a carrier frequency of the selected channel signal;

converting, using the radio receiver module, the selected one of the plurality of channel signals into an output signal;

down-sampling, in response to the control signal, the output signal to produce a down-sampled digital signal at a frequency that is a non-integer multiple of a carrier frequency of the selected channel signal;

generating a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals, wherein the first interface clock frequency, and each integer multiple of the first interface clock frequency, are non-integer multiples of the carrier frequency of the selected one of the plurality of channel signals; and

driving a device interface to couple a device to the radio receiver module based on the first interface clock, wherein the device interface is a bidirectional interface that is configured to exchange control data between the radio receiver module and the device.

17. The method of claim 16 wherein driving the device interface includes producing a device interface signal that is clocked at the first interface clock frequency.

18. The method of claim 17 wherein the device interface signal includes an audio channel signal.

19. The method of claim 16 wherein driving the device interface includes sampling a device interface signal at the first interface clock frequency.

20. The method of claim 19 wherein the device interface signal includes control data.

21. The method of claim 16 wherein generating the first interface clock includes:

producing a first divisor that varies based on the carrier frequency of the selected one of the plurality of channel signals; and

producing the first interface clock by dividing a reference oscillation by the first divisor.

22. The method of claim 21 wherein the first divisor includes a fraction.

23. The method of claim 21 wherein generating the first interface clock further includes:

producing a second divisor that varies based on the carrier frequency of the selected one of the plurality of channel signals; and

producing a second interface clock by dividing the reference oscillation by the second divisor.

24. The method of claim 16 wherein generating the first interface clock includes:

producing the first interface clock by dividing a local oscillation signal by a first divisor.

25. The method of claim 24 wherein the first divisor includes a fraction.

26. The method of claim 24 wherein generating the first interface clock further includes:

producing a second interface clock by dividing the local oscillation signal by a second divisor.

27. The method of claim 16 wherein the device interface is an integrated circuit device.

28. The method of claim 16 wherein the first interface clock frequency is less than the carrier frequency of the selected one of the plurality of channel signals.