Calibrating a phase detector and analog-to-digital converter offset and gain

• US 8,130,888 B2
• Filed: 09/18/2009
• Issued: 03/06/2012
• Est. Priority Date: 12/29/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Eldredge, Adam B., Batchelor, Jeffrey S., Hammes, Gary
• Primary Examiner(s): Kim, Kevin
• Application Number:
  US12/562,360
• Publication Number:
  US 20100008459A1
• Time in Patent Office: 900 Days
• Field of Search: 375/355, 375/326
• US Class Current: 375/355
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.

Claims

1. A method comprising:

sweeping a phase of a sampling clock across a data eye during calibration of a phase detector;

filtering a value corresponding to an output of the phase detector;

inserting a calibration signal corresponding to the filtered value into the phase detector;

adjusting the calibration signal until the filtered value is substantially zero; and

storing a phase adjust value corresponding to the adjusted calibration signal.

2. The method of claim 1 further comprising applying the phase adjust value to the phase detector.

3. The method of claim 1, further comprising simulating data transitions for incoming data to the phase detector during calibration.

4. The method of claim 3, further comprising simulating the data transitions if actual data transitions are below a predetermined value.

5. The method of claim 4, further comprising measuring the actual data transitions using an error sampler.

6. An apparatus comprising:

a phase detector to generate a phase detector pulse and sweep a phase of a sampling clock across a data eye during calibration of the phase detector;

an analog-to-digital converter (ADC) coupled to receive the phase detector pulse;

a calibration loop coupled to receive an output of the ADC and to generate a phase adjust value to remove an offset between a reference current and an error current corresponding to the phase detector pulse; and

a storage to store the phase adjust value.

7. The apparatus of claim 6, wherein the phase adjust value is to force an average value of the ADC output to be substantially zero.

8. The apparatus of claim 6, wherein the calibration loop comprises:

a filter to receive the ADC output; and

an inverting gain stage coupled to an output of the filter.

9. The apparatus of claim 6, wherein the phase detector comprises a multiplier to combine the phase adjust value with an error pulse or a reference pulse.

10. The apparatus of claim 6, further comprising a multiplexer coupled to the phase detector to provide incoming data or an asynchronous clock to the phase detector.

11. The apparatus of claim 10, wherein the multiplexer is to provide the asynchronous clock to the phase detector if the incoming data has less than a predetermined amount of transitions.

12. The apparatus of claim 6, wherein the phase detector comprises:

a first latch to receive incoming data and having a first delay; and

a delay element to receive the incoming data, the delay element unmatched to the first delay.

13. A system comprising:

an amplifier to receive optical energy and convert the optical energy to electrical energy;

a phase detector coupled to the amplifier to receive and sweep a phase of a sampling clock across a data eye during calibration of the phase detector, and generate a phase detector pulse obtained from an error pulse and a reference pulse;

an analog-to-digital converter (ADC) coupled to receive the phase detector pulse;

a calibration loop coupled to receive an output of the ADC and to generate a phase adjust value; and

a transition detector to detect an amount of data transitions during the calibration.

14. The system of claim 13, wherein the phase adjust value is to force a filtered value of the ADC output to be substantially zero.

15. The system of claim 13, wherein the phase detector comprises:

a first latch to receive incoming data and having a first delay; and

a delay element to receive the incoming data, the delay element unmatched to the first delay.

16. The system of claim 13, further comprising a multiplexer to receive a control signal from the transition detector and to select incoming data or a transition simulator for input into the phase detector.