BIAS voltage generation circuit for an SOI radio frequency switch

• US 8,131,225 B2
• Filed: 12/23/2008
• Issued: 03/06/2012
• Est. Priority Date: 12/23/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Botula, Alan B., Nowak, Edward J.
• Primary Examiner(s): Nguyen, Khai M
• Application Number:
  US12/342,335
• Publication Number:
  US 20100156511A1
• Time in Patent Office: 1,169 Days
• Field of Search: 455/78, 455/83, 455/127.1, 333103-104
• US Class Current: 455/78
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A radio frequency (RF) switch located on a semiconductor-on-insulator (SOI) substrate includes at least one electrically biased region in a bottom semiconductor layer. The RF switch receives an RF signal from a power amplifier and transmits the RF signal to an antenna. The electrically biased region may be biased to eliminate or reduce accumulation region, to stabilize a depletion region, and/or to prevent formation of an inversion region in the bottom semiconductor layer, thereby reducing parasitic coupling and harmonic generation due to the RF signal. A voltage divider circuit and a rectifier circuit generate at least one bias voltage of which the magnitude varies with the magnitude of the RF signal. The at least one bias voltage is applied to the at least one electrically biased region to maintain proper biasing of the bottom semiconductor layer to minimize parasitic coupling, signal loss, and harmonic generation.

Claims

1. A method of operating a semiconductor circuit comprising:

providing a semiconductor circuit including;

a radio frequency (RF) switch including at least one field effect transistor located on a semiconductor-on-insulator (SOI) substrate;

a radio frequency (RF) signal line for transmitting a radio frequency (RF) signal, wherein said RF signal line is connected to said RF switch; and

a circuitry that generates, from said RF signal, at least one bias voltage having a time-dependent modulated magnitude that is proportional to a time-dependent magnitude of said RF signal, and changes over a time scale that is at least one order of magnitude greater than a period of said RF signal; and

supplying said at least one bias voltage to a bottom semiconductor layer underlying a buried insulator layer of said SOI substrate.

2. The method of claim 1, wherein said semiconductor circuit further comprises at least one bias voltage feed line that supplies said at least one bias voltage to said bottom semiconductor layer of said SOI substrate.

3. The method of claim 1, wherein said semiconductor circuit further comprises at least one conductive via resistively connected to said bottom semiconductor layer, and wherein said at least one bias voltage is provided to said bottom semiconductor layer through said at least one conductive via.

4. The method of claim 1, wherein said at least one bias voltage includes a positive bias voltage having a magnitude greater than a magnitude of a maximum positive swing of said RF signal within a period of said RF signal, and wherein said at least one bias voltage includes a negative bias voltage having a magnitude greater than a magnitude of a maximum negative swing of said RF signal within a period of said RF signal.

5. The method of claim 1, wherein said semiconductor circuit further comprises a power amplifier which is connected to, and provides said RF signal to, said RF signal line.

6. The method of claim 1, wherein said at least one bias voltage is generated by a voltage divider that comprises a serial connection of a first set of at least one impedance element having a first impedance and a second set of at least one impedance element having a second impedance, wherein one end of said first set of at least one impedance element is directly connected to said RF signal line, and wherein one end of said second set of at least one impedance element is directly connected to electrical ground.

7. The method of claim 1, wherein said semiconductor circuit further comprises:

at least one first doped semiconductor region embedded in said bottom semiconductor layer and having a p-type doping; and

at least one second doped semiconductor region embedded in said bottom semiconductor layer and having an n-type doping.

8. The method of claim 7, wherein said semiconductor circuit further comprises a rectification circuit, and said method further comprises:

applying a negative bias voltage that said rectification circuit generates from said RF signal to said at least one first doped semiconductor region; and

applying a positive bias voltage that said rectification circuit generates from said RF signal is applied to said at least one second doped semiconductor region.

9. The method of claim 8, further comprising:

suppressing formation of an accumulation region in which majority charge carriers accumulate in said bottom semiconductor layer with one of said negative bias voltage and said positive bias voltage; and

suppressing formation of an inversion region in which minority charge carriers accumulate in said bottom semiconductor layer with the other of said negative bias voltage and said positive bias voltage.

10. A semiconductor circuit comprising:

a radio frequency (RF) switch including at least one field effect transistor located on a semiconductor-on-insulator (SOI) substrate;

a radio frequency (RF) signal line for transmitting a radio frequency (RF) signal, wherein said RF signal line is connected to said RF switch;

a voltage divider connected between said RF signal line and electrical ground;

a rectification circuit connected to said voltage divider and generating, from said RF signal, at least one bias voltage having a time-dependent modulated magnitude that is proportional to a time-dependent magnitude of said RF signal, and changes over a time scale that is at least one order of magnitude greater than a period of said RF signal; and

at least one bias voltage feed line providing said at least one bias voltage to a bottom semiconductor layer underlying a buried insulator layer of said SOI substrate.

11. The semiconductor circuit of claim 10, further comprising at least one conductive via resistively connected to said bottom semiconductor layer, wherein said at least one bias voltage is provided to said bottom semiconductor layer through said at least one conductive via.

12. The semiconductor circuit of claim 10, wherein said at least one bias voltage includes a positive bias voltage having a magnitude greater than a magnitude of a maximum positive swing of said RF signal within a period of said RF signal.

13. The semiconductor circuit of claim 10, wherein said at least one bias voltage includes a negative bias voltage having a magnitude greater than a magnitude of a maximum negative swing of said RF signal within a period of said RF signal.

14. The semiconductor circuit of claim 10, wherein said at least one bias voltage includes a positive bias voltage having a magnitude greater than a magnitude of a maximum positive swing of said RF signal within a period of said RF signal, and wherein said at least one bias voltage includes a negative bias voltage having a magnitude greater than a magnitude of a maximum negative swing of said RF signal within a period of said RF signal.

15. The semiconductor circuit of claim 10, further comprising a power amplifier which is connected to, and provides said RF signal to, said RF signal line.

16. The semiconductor circuit of claim 10, wherein said voltage divider comprises a serial connection of a first set of at least one impedance element having a first impedance and a second set of at least one impedance element having a second impedance, wherein one end of said first set of at least one impedance element is directly connected to said RF signal line, and wherein one end of said second set of at least one impedance element is directly connected to electrical ground, and wherein a common node between said first set and said second set is directly connected to an input node of said rectification circuit.

17. The semiconductor circuit of claim 16, wherein each of said first set of at least one impedance element and said second set of at least one impedance element comprises at least one of a resistor, a capacitor, and an inductor.

18. The semiconductor circuit of claim 16, wherein a ratio between a magnitude of a sum of said first impedance and said second impedance to a magnitude of said second impedance is from about 0.5 to 1.0 at a frequency of said RF signal.

19. The semiconductor circuit of claim 16, wherein said rectification circuit comprises at least one resistor directly connected to electrical ground, at least one capacitor directly connected to electrical ground, at least one diode directly connected to electrical ground, and at least another diode directly connected to said input node of said rectification circuit.

20. The semiconductor circuit of claim 10, further comprising:

at least one first doped semiconductor region embedded in said bottom semiconductor layer and having a p-type doping, wherein a negative bias voltage that said rectification circuit generates from said RF signal is applied to said at least one first doped semiconductor region; and

at least one second doped semiconductor region embedded in said bottom semiconductor layer and having an n-type doping, wherein a positive bias voltage that said rectification circuit generates from said RF signal is applied to said at least one second doped semiconductor region.

21. A machine readable medium embodying a design structure for designing, manufacturing, or testing a design for a semiconductor structure, said design structure comprising:

a first data representing a radio frequency (RF) switch including at least one field effect transistor located on a semiconductor-on-insulator (SOI) substrate;

a second data representing a radio frequency (RF) signal line for transmitting a radio frequency (RF) signal, wherein said RF signal line is connected to said RF switch;

a third data representing a voltage divider connected between said RF signal line and electrical ground;

a fourth data representing a rectification circuit connected to said voltage divider and generating, from said RF signal, at least one bias voltage having a time-dependent modulated magnitude that is proportional to a time-dependent magnitude of said RF signal, and changes over a time scale that is at least one order of magnitude greater than a period of said RF signal; and

a fifth data representing at least one bias voltage feed line providing said at least one bias voltage to a bottom semiconductor layer underlying a buried insulator layer of said SOI substrate.

22. The machine readable medium of claim 21, further comprising an additional data representing at least one conductive via resistively connected to said bottom semiconductor layer, wherein said at least one bias voltage is provided to said bottom semiconductor layer through said at least one conductive via.

23. The machine readable medium of claim 21, further comprising:

a sixth data representing an antenna for transmitting said RF signal; and

a seventh data representing another RF signal line connected to said RF switch and said antenna.

24. The machine readable medium of claim 21, wherein said third data includes a eighth data representing a first set of at least one impedance element having a first impedance, a ninth data representing a second set of at least one impedance element having a second impedance, and a tenth data representing a serial connection between said first set of at least one impedance element and said second set of at least one impedance element, wherein one end of said first set of at least one impedance element is directly connected to said RF signal line, and wherein one end of said second set of at least one impedance element is directly connected to electrical ground, and wherein a common node between said first set and said second set is directly connected to an input node of said rectification circuit.

25. The machine readable medium of claim 21, further comprising:

a first additional data representing at least one first doped semiconductor region embedded in said bottom semiconductor layer and having a p-type doping;

a second additional data representing a first electrical wiring structure for supplying a negative bias voltage that said rectification circuit generates from said RF signal to said at least one first doped semiconductor region;

a third additional data representing at least one second doped semiconductor region embedded in said bottom semiconductor layer and having an n-type doping; and

a fourth additional data representing a second electrical wiring structure for supplying a positive bias voltage that said rectification circuit generates from said RF signal to said at least one second doped semiconductor region.