Selective broadcasting of data in series connected devices

• US 8,131,913 B2
• Filed: 10/20/2008
• Issued: 03/06/2012
• Est. Priority Date: 02/04/2008
• Status: Expired due to Fees

• Current Assignee: NovaChips Canada Inc. (NovaChips Co., Ltd.)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Pyeon, Hong Beom
• Primary Examiner(s): Dudek, Jr, Edward
• Assistant Examiner(s): Verderamo, III, Ralph A
• Application Number:
  US12/254,315
• Publication Number:
  US 20090198857A1
• Time in Patent Office: 1,233 Days
• Field of Search: 711/103, 711/154, 711/200, 711/5, 711/E12.001
• US Class Current: 711/103
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique identification number (ID). The memory controller designates the subset of devices to execute the command, excluding the non-selected devices from executing the command. The memory controller encodes the ID numbers of the designated devices into a single coded address, and sends the command along with the coded address in a packet to the series connected devices. Each device receives the packet in a serial bitstream and decodes the coded address using its ID number in order to determine whether it is selected or not. If the device is selected, the command is executed. Otherwise, the packet is forwarded without executing the command.

Claims

1. A method for selecting a subset of devices of a plurality of devices serial-connected to a memory controller to execute a command, comprising:

encoding identification (ID) numbers of each of the subset of devices for providing code information by performing mathematical operations to logically combine the ID numbers of the subset of devices to generate a mask;

providing a command packet including an op code and the code information to each of the plurality of devices;

decoding the code information received by each of the plurality of devices by, at each device, performing a mathematical operation on the mask and an ID number stored in the device, to determine if the mask encodes the ID number stored in the device; and

executing the op code if the ID number stored in the device is encoded in the received code information.

2. The method according to claim 1, wherein the memory controller provides 2x of the ID numbers, where x is an integer greater than zero.

3. The method according to claim 1, wherein each of the ID numbers is N-bits in length, and the code information includes a Target ID number N-bits in length and the mask code N-bits in length, where N is an integer value greater than 0.

4. The method according to claim 3, wherein the step of encoding comprises:

selecting one ID number of the subset of devices as the Target ID number;

comparing the ID numbers of each of the subset of devices with the Target ID number for generating corresponding coded ID numbers; and

logically combining a bit in the same bit position from each of the coded ID numbers for generating one bit having the corresponding bit position in the mask code.

5. The method according to claim 4, wherein there are M ID numbers corresponding to the subset of devices, where M is an integer value greater than 0.

6. The method according to claim 5, wherein the step of comparing comprises steps of:

outputting the comparison results in an M*N matrix; and

transposing the M*N matrix into an N*M matrix.

7. The method according to claim 6, wherein the one bit is generated by executing a logical function upon the comparison results in one of the N rows of the N*M matrix.

8. The method according to claim 7, wherein a first bit of the mask code generated from the first row of the N*M matrix represents a most significant bit of the mask code, and a last bit of the mask code generated from the last row of the N*M matrix represents a least significant bit of the mask code.

9. The method according to claim 4, wherein the step of comparing comprises a step of executing an XNOR function between the ID numbers of each of the subset of devices with the Target ID number.

10. The method according to claim 4, wherein the step of logically combining comprises a step of executing a NAND function between bits in the same bit position from each of the coded ID numbers.

11. The method according to claim 4, wherein the step of decoding comprises a step of processing the ID number stored in the device with the Target ID number and the mask code to provide an indication that all bit positions of the ID number stored in the device are encoded in the mask code.

12. The method according to claim 11, wherein the step of processing comprises

comparing bits of each bit position of the ID number stored in the device with the corresponding bits of each corresponding bit position of the Target ID number for generating a coded target ID number;

adding the mask code to the coded target ID number for providing a modified coded target ID number; and

multiplying the bits of the modified coded target ID number with each other to provide the indication that all bit positions of the ID number stored in the device are encoded in the mask.

13. The method according to claim 12, wherein the step of comparing the bits of each bit position of the ID number stored in the device comprises a step of executing an XNOR logic function;

the step of adding the mask code to the coded target ID number comprises a step of executing an OR logic function; and

the step of multiplying the bits of the modified coded target ID number comprises a step of executing an AND logic function.

14. The method according to claim 3, wherein the step of providing the command packet comprises steps where each of the plurality of devices receives the command packet from one of a previous device and the memory controller, and passes the command packet to one of a subsequent device and the memory controller, the previous device and the subsequent device including memory devices.

15. The method according to claim 14, further comprises a step of inhibiting the command packet from being passed to one of the subsequent device and the memory controller when the last device of the subset of devices decodes the code information.

16. The method according to claim 15, wherein the step of inhibiting comprises steps of:

logically combining the Target ID number, the mask code and the ID number stored in the device to provide a last device signal; and

setting an output buffer to a null value in response to the last device signal.

17. The method according to claim 16, wherein the step of logically combining comprises steps of:

adding the Target ID number to the mask code to obtain a last designated device address; and

comparing the last designated device address to the ID number stored in the device, the last device signal being generated when the last designated device address matches the ID number stored in the device.

18. The method according to claim 16, wherein the step of setting comprises a step of coupling an input of the output buffer to a static logic level in response to the last device signal.

19. A memory device having a device identification (ID) number for receiving a command packet comprising:

a data flow-through path for receiving the command packet at an input port and for passing the command packet to an output port, the command packet including an op code and code information corresponding to a subset of device ID numbers selected for executing the op code, the code information being generated by performing mathematical operations to logically combine the subset of device ID numbers to generate a mask;

a command interpreter selectively enabled for decoding the op code; and

an ID processor for receiving the code information and decoding the code information, by performing a mathematical operation on the mask and an ID number stored in the memory device, to determine if the mask encodes the ID number stored in the memory device for enabling the command interpreter if the device ID number is encoded in the code information.

20. The memory device of claim 19, wherein the data flow-through path comprises:

an input buffer coupled to the input port for buffering the command packet; and

an output buffer coupled to the input buffer for receiving the command packet and for driving the command packet onto the output port.

21. The memory device of claim 20, wherein the code information includes the mask code and a Target ID number, the ID processor including an ID match decoder for logically combining the mask code, the Target ID number and the device ID for providing a match signal when the device ID number is encoded in the mask code.

22. The memory device according to claim 21, wherein the Target ID number is one of the subset of device ID numbers.

23. The memory device according to claim 21, wherein the ID match decoder comprises

a comparator for comparing each bit of the device ID number with a corresponding bit of the Target ID number to provide a coded Target ID number;

an adder for adding each bit of the mask code to a corresponding bit of the coded Target ID number to provide a modified coded target ID number; and

a multiplier for providing the match signal when all bits of the modified coded target ID number are at an active logic level.

24. The memory device according to claim 23, wherein the comparator includes XNOR logic gates, each XNOR logic gate comparing one bit of the device ID number with a corresponding bit of the Target ID number.

25. The memory device according to claim 23, wherein the adder includes OR logic gates, each OR logic gate adding one bit of the mask code to a corresponding bit of the coded Target ID number.

26. The memory device according to claim 23, wherein the multiplier includes an AND logic circuit for receiving all bits of the modified coded target ID number.

27. The memory device according to claim 21, wherein the ID processor includes an output inhibiting circuit for inhibiting the command packet from being driven onto the output port.

28. The memory device according to claim 27, wherein the output inhibiting circuit comprises:

an adder for adding the mask code to the Target ID number to provide a last device ID number of the subset of device ID numbers; and

a last ID decoder for comparing the device ID number to the last device ID number and for providing a last ID control signal when the device ID number matches the last device ID number.

29. The memory device according to claim 28, wherein the output buffer is disabled in response to the last ID control signal.

30. The memory device according to claim 28, wherein the data flow-through path includes a selector for selectively passing one of the command packet and a null value to the output buffer, the selector passing the null value in response to the last ID control signal.

31. The memory device according to claim 30, wherein the null value corresponds to a bit stored in an output data register coupled to the selector.

32. A memory system comprising:

a memory controller for issuing a command packet including an op code and code information corresponding to a subset of device identification (ID) numbers selected for executing the op code, the code information being generated by performing mathematical operations to logically combine the subset of device ID numbers to generate a mask; and

a plurality of serial-connected memory devices in a ring topology with the memory controller, each of the plurality of memory devices having a unique device ID number and receiving the command packet, decoding the code information by performing a mathematical operation on the mask and the unique device ID number, to determine if the mask encodes the unique device ID number and executing the op code if the unique device ID number is encoded in the code information.

33. The memory system of claim 32, wherein each of the plurality of memory devices comprises

a data flow-through path for receiving the command packet at an input port and for passing the command packet to an output port;

a command interpreter selectively enabled for decoding the op code; and

an ID processor for receiving the code information and decoding the code information for enabling the command interpreter when the unique device ID number is encoded in the code information.

34. The memory system of claim 33, wherein the code information comprises the mask code and a Target ID number, the ID processor including an ID match decoder for logically combining the mask code, the Target ID number and the device ID number to provide a match signal when the unique device ID number is encoded in the mask code.

35. The memory system of claim 34, wherein the ID processor comprises an output inhibiting circuit for inhibiting the command packet from being driven onto the output port when the unique device ID number matches a last device ID number of the subset of device ID numbers.