Techniques for generating clock signals using counters

• US 8,132,039 B1
• Filed: 10/31/2007
• Issued: 03/06/2012
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Nguyen, Andy
• Primary Examiner(s): DU, THUAN N
• Application Number:
  US11/931,235
• Time in Patent Office: 1,588 Days
• Field of Search: 713/500, 713/501, 713/600, 327/156, 377/39
• US Class Current: 713/501
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom

Abstract

The circuit, typically a delay-locked loop, comprises a phase detector, a first counter, a second counter, and a comparator. The phase detector compares a phase of a first clock signal with a phase of a second clock signal. The first counter generates first count signals and adjusts the first count signals when the phase detector indicates that the phases of the first and the second clock signals are out of alignment. The second counter generates second count signals. The first comparator generates a first comparison signal in response to a comparison between the first count signals and the second count signals. The second clock signal is generated in response to the first comparison signal.

Claims

1. A circuit comprising:

a phase detector that compares a phase of a first clock signal to a phase of a second clock signal;

a first counter that generates first count signals based on an output of the phase detector;

a second counter that generates second count signals;

a first comparator that generates a first comparison signal based on the first count signals and the second count signals, wherein the second clock signal is based on the first comparison signal;

a first oscillator that generates a first oscillator signal, wherein the second counter generates the second count signals based on the first oscillator signal;

a third counter that generates third count signals; and

a second comparator that generates a second comparison signal based on the first count signals and the third count signals, wherein the first oscillator generates oscillations in the first oscillator signal based on the second comparison signal.

2. The circuit defined in claim 1 further comprising:

a second oscillator that generates a second oscillator signal, wherein the third counter generates the third count signals based on the second oscillator signal;

a fourth counter that generates fourth count signals; and

a third comparator that generates a third comparison signal based on the first count signals and the fourth count signals, wherein the second oscillator generates oscillations in the second oscillator signal based on the third comparison signal.

3. The circuit defined in claim 2 further comprising:

a flip-flop that stores a logic state of the first comparison signal as the second clock signal for transmission to the phase detector.

4. The circuit defined in claim 1 wherein the phase detector changes a logic state of one of first and second output signals when the phases of the first and the second clock signals are out of alignment, and the phase detector changes a logic state of a third output signal when the phases of the first and the second clock signals are aligned.

5. The circuit defined in claim 1 wherein the first counter is an up/down counter that is configured to increase and decrease a binary value of the first count signals in response to a first output signal of the phase detector.

6. The circuit defined in claim 1 wherein the circuit is fabricated on a programmable logic integrated circuit.

7. The circuit defined in claim 1 wherein the circuit comprises a delay-locked loop circuit.

8. A circuit comprising:

a phase detector that compares a phase of a first clock signal to a phase of a second clock signal;

a first counter that generates first count signals and that adjusts the first count signals when the phase detector indicates that the phases of the first and the second clock signals are out of alignment;

a second counter that generates second count signals;

a first comparator that generates a first comparison signal in response to a comparison between the first count signals and the second count signals, wherein the second clock signal is generated in response to the first comparison signal;

a first oscillator that generates a first oscillator signal, wherein the second counter adjusts the second count signals in response to the first oscillator signal;

a third counter that generates third count signals;

a second oscillator that generates a second oscillator signal, wherein the third counter adjusts the third count signals in response to the second oscillator signal; and

a second comparator that generates a second comparison signal in response to a comparison between at least a subset of the first count signals and the third count signals, wherein the first oscillator is enabled to generate oscillations in the first oscillator signal in response to the second comparison signal.

9. The circuit defined in claim 8 further comprising:

a fourth counter that generates fourth count signals;

a third oscillator that generates a third oscillator signal, wherein the fourth counter adjusts the fourth count signals in response to the third oscillator signal; and

a third comparator that generates a third comparison signal in response to a comparison between the first count signals and the fourth count signals, wherein the second oscillator is enabled to generate oscillations in the second oscillator signal in response to the third comparison signal.

10. A circuit comprising:

a phase detector that compares a phase of a first clock signal to a phase of a second clock signal;

a first counter that generates first count signals and that adjusts the first count signals when the phase detector indicates that the phases of the first and the second clock signals are out of alignment;

a second counter that generates second count signals;

a first comparator that generates a first comparison signal in response to a comparison between the first count signals and the second count signals, wherein the second clock signal is generated in response to the first comparison signal; and

a third counter that generates a third clock signal by dividing a frequency of the first clock signal, wherein the first counter adjusts the first count signals in response to the third clock signal when the phases of the first and the second clock signals are out of alignment.

11. A circuit comprising:

a phase detector that compares a phase of a first clock signal with a phase of a second clock signal;

a first counter that generates first count signals, wherein the first counter varies the first count signals to adjust the phase of the second clock signal and align the phases of the first and the second clock signals;

a first oscillator that generates a first oscillator signal having a frequency that is independent of variations in a phase offset between the first and the second clock signals;

a second counter that generates second count signals, wherein the second counter adjusts the second count signals in response to the first oscillator signal; and

a first comparator that generates a first comparison signal in response to a comparison between the first count signals and the second count signals, wherein the second clock signal is generated in response to the first comparison signal.

12. The circuit defined in claim 11 wherein the first counter increases a binary value of the first count signals to adjust the phase of the second clock signal in a first direction and decreases the binary value of the first count signals to adjust the phase of the second clock signal in a second direction.

13. The circuit defined in claim 11 wherein the circuit further comprises:

a third counter that generates third count signals;

a second oscillator that generates a second oscillator signal, wherein the third counter adjusts the third count signals in response to the second oscillator signal; and

a second comparator that generates a second comparison signal in response to a comparison between the first count signals and the third count signals, wherein the first oscillator is enabled to generate oscillations in the first oscillator signal in response to the second comparison signal.

14. The circuit defined in claim 13 wherein the first oscillator varies the frequency of the first oscillator signal in response to a first select signal, and the second oscillator varies a frequency of the second oscillator signal in response to a second select signal.

15. The circuit defined in claim 13 wherein the first oscillator varies a delay of the first oscillator signal in response to a first select signal, and the second oscillator varies a delay of the second oscillator signal in response to a second select signal.

16. The circuit defined in claim 11 wherein the first counter changes the first count signals in response to first and second output signals of the phase detector when the phases of the first and the second clock signals move out of alignment, and wherein the first counter maintains the first count signals constant in response to the first and the second output signals of the phase detector when the phases of the first and the second clock signals are aligned.

17. The circuit defined in claim 16 wherein the phase detector changes a logic state of one of the first and the second output signals when the phases of the first and the second clock signals move out of alignment, and the phase detector changes a logic state of a third output signal when the phases of the first and the second clock signals become aligned.

18. The circuit defined in claim 11 wherein the first counter increases a binary value of the first count signals to cause rising edges of the second clock signal to occur later in time, and decreases the binary value of the first count signals to cause rising edges of the second clock signal to occur sooner in time.

19. The circuit defined in claim 11 wherein the circuit further comprises:

a third counter that generates a third clock signal by dividing a frequency of the first clock signal, wherein the first counter adjusts the first count signals in response to the third clock signal when the phases of the first and the second clock signals are out of alignment.

20. The circuit defined in claim 11 wherein the circuit comprises a delay-locked loop circuit.

21. A method for generating an output clock signal, the method comprising:

comparing a phase of a first clock signal with a phase of a second clock signal;

generating first count signals;

varying the first count signals when the phases of the first and the second clock signals are out of alignment;

generating second count signals;

generating a first comparison signal in response a comparison between the first count signals and the second count signals;

generating the second clock signal in response to the first comparison signal;

generating a first oscillator signal;

varying the second count signals in response to the first oscillator signal;

generating third count signals;

generating a second comparison signal based on a comparison between at least a subset of the first count signals and the third count signals; and

enabling an oscillator to generate oscillations in the first oscillator signal based on the second comparison signal.

22. The method defined in claim 21 further comprising:

generating a second oscillator signal; and

varying the third count signals in response to the second oscillator signal.

23. The method defined in claim 21 wherein varying the first count signals when the phases of the first and the second clock signals are out of alignment further comprises increasing a binary value of the first count signals to adjust the phase of the second clock signal in a first direction and decreasing the binary value of the first count signals to adjust the phase of the second clock signal in a second direction to align the phases of the first and the second clock signals, wherein the first count signals are maintained at constant values when the phases of the first and the second clock signals are aligned.

24. A method comprising:

comparing a phase of a first clock signal with a phase of a second clock signal using a phase detector;

varying first count signals generated by a first counter based on an output of the phase detector;

generating a first oscillator signal;

generating second count signals based on the first oscillator signal using a second counter;

generating a first comparison signal based on the first count signals and the second count signals, wherein the second clock signal is generated in response to the first comparison signal;

generating third count signals using a third counter; and

generating a second comparison signal based on the first count signals and the third count signals, wherein generating a first oscillator signal comprises generating oscillations in the first oscillator signal based on the second comparison signal.