Semiconductor device having different structures formed simultaneously

• US 8,133,783 B2
• Filed: 10/21/2008
• Issued: 03/13/2012
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Gogoi, Bishnu P.
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Luke, Daniel
• Application Number:
  US12/255,424
• Publication Number:
  US 20090261396A1
• Time in Patent Office: 1,239 Days
• Field of Search: 438/201, 438/210, 438/209, 438/267, 438/304, 438/596, 438/275, 257/500, 257/501, 257/E21.681, 257/E27.016
• US Class Current: 438/267
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Claims

1. A method to form an integrated circuit, the method comprising:

forming a first portion of an active device wherein the active device is a higher voltage higher frequency non-symmetrical analog transistor and comprises a plurality of doped regions in a semiconductor material;

forming a first portion of a lower voltage digital CMOS device;

forming a first portion of a passive device;

forming a first portion of a memory device; and

forming a dielectric structure;

wherein the first portion of the active device, the first portion of the lower voltage digital CMOS device, the first portion of the passive device, or the first portion of the memory device, or combinations thereof, are formed simultaneously or nearly simultaneously;

wherein the higher frequency of the active device is based at least in part on a relatively shorter channel length of the active device, wherein the channel length of the active device is a function of a deposition thickness of a gate material of the active device;

wherein the dielectric structure extends from a surface of the semiconductor material to a distance below all of the doped regions of the plurality of doped regions of the active device;

wherein the memory device has a doped region;

wherein the dielectric structure is between the plurality of doped regions of the active device and the doped region of the memory device and the dielectric structure surrounds the plurality of doped regions of the active device; and

wherein at least a portion of the passive device is disposed over the dielectric structure.

2. The method of claim 1, wherein:

the active device is a transistor having a control electrode, the passive device is a capacitor having a first plate, and the memory device is a non-volatile memory (NVM) device having a control electrode;

wherein said forming the first portion of the active device, forming the first portion of the passive device, or forming the first portion of the memory device, or combinations thereof, comprise forming the control electrode of the transistor, the control electrode of the NVM device, or the first plate of the capacitor, or combinations thereof simultaneously or nearly simultaneously.

3. An integrated circuit, comprising:

an active device having a first portion and a plurality of doped regions in a semiconductor material, wherein the active device comprises a higher voltage higher frequency non-symmetrical analog transistor;

a lower voltage digital CMOS device having a first portion;

a passive device having a first portion;

a memory device having a first portion; and

a dielectric structure extending from a surface of the semiconductor material to a distance below all or nearly all of the doped regions of the plurality of doped regions of the active device;

wherein the first portion of the active device, the first portion of the lower voltage digital CMOS device, the first portion of the passive device, or the first portion of the memory device, or combinations thereof, are formed simultaneously or nearly simultaneously;

wherein the higher frequency of the active device is based at least in part on a relatively shorter channel length of the active device, wherein the channel length of the active device is a function of a deposition thickness of a gate material of the active device;

wherein the memory device has a doped region;

wherein the dielectric structure is disposed between the plurality of doped regions of the active device and the doped region of the memory device;

wherein the dielectric structure at least partially surrounds the plurality of doped regions of the active device; and

wherein at least a portion of the passive device is disposed over the dielectric structure.

4. The integrated circuit of claim 3,

wherein the active device comprises a transistor having a control electrode, the passive device is a capacitor having a first plate, and the memory device is a non-volatile memory (NVM) device having a control electrode;

wherein the control electrode of the transistor, the control electrode of the NVM device, or the first plate of the capacitor, or combinations thereof, are formed simultaneously or nearly simultaneously.