Short-channel silicon carbide power mosfet

• US 8,133,789 B1
• Filed: 05/08/2009
• Issued: 03/13/2012
• Est. Priority Date: 04/11/2003
• Status: Active Grant

• Current Assignee: Purdue Research Foundation (Purdue University)
• Original Assignee: Purdue Research Foundation (Purdue University)
• Inventors: Cooper, James A., Matin, Maherin
• Primary Examiner(s): Sefer, A.
• Application Number:
  US12/463,054
• Time in Patent Office: 1,040 Days
• Field of Search: 438/105, 438/275, 438/931, 438/285, 257/327
• US Class Current: 438/285
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0475 Changing the shape of the semiconductor body, e.g. forming recesses, etching of the semiconductor body H01L21/302
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

A silicon carbide power MOSFET having a drain region of a first conductivity type, a base region of a second conductivity type above the drain region, and a source region of the first conductivity type adjacent an upper surface of the base region, the base region including a channel extending from the source region through the base region adjacent a gate interface surface thereof, the channel having a length less than approximately 0.6 μm, and the base region having a doping concentration of the second conductivity type sufficiently high that the potential barrier at the source end of the channel is not lowered by the voltage applied to the drain. The MOSFET includes self-aligned base and source regions as well as self-aligned ohmic contacts to the base and source regions.

Claims

1. A method of fabricating a silicon carbide power DMOSFET, comprising:

providing a silicon carbide drain region of a first conductivity type;

forming a silicon carbide base region of a second conductivity type above said drain region;

forming a silicon carbide source region of said first conductivity type adjacent an upper surface of said base region;

creating a channel extending from said source region through said base region adjacent a gate interface surface thereof, said channel having a length less than approximately 0.6 μ

m; and

creating self-aligned base and source ohmic contacts;

wherein said base region has a doping concentration of said second conductivity type sufficiently high that a potential barrier at the source end of the channel is not lowered by a voltage applied to the drain; and

wherein said base region is formed by ion implantation using a polysilicon mask and said source region is subsequently formed in said upper surface of said base region by ion implantation using an implant mask formed by oxidation of the polysilicon mask.

2. The method of claim 1, further comprising forming a counter-doped surface layer in said channel region by implanting dopant atoms of said first conductivity type into said base region after formation thereof, said counter-doped layer configured to control the threshold voltage.

3. The method of claim 2, wherein said counter-doping is introduced with the same mask used for doping of said base region.

4. The method of claim 3, further comprising forming a silicon carbide drift layer of said first conductivity type between said base region and said drain region.

5. The method of claim 4, wherein said first conductivity type is n-type and said second conductivity type is p-type.

6. The method of claim 1, further comprising providing said channel region with a surface doping concentration of said first conductivity type of about 1-3×

10¹⁷ cm<sup>−

3</sup>, and a doping concentration of said second conductivity type of at least about 2.5×

10¹⁷ cm<sup>−

3</sup> in a lower portion of said channel region.

7. The method of claim 6, wherein the bottom of said base region has a doping concentration of said second conductivity type of at least about 1×

10¹⁸ cm<sup>−

3</sup>.

8. The method of claim 7, wherein said doping of said channel region is performed by ion implantation after formation of said base region.