Layered chip package
First Claim
Patent Images
1. A layered chip package comprising:
- a main body having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; and
a wiring disposed on the first side surface of the main body, wherein;
the main body includes a plurality of layer portions stacked;
each of the plurality of layer portions includes a semiconductor chip having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions;
the second, third and fourth side surfaces of the semiconductor chip are respectively located at the second, third and fourth side surfaces of the main body;
the first side surface of the semiconductor chip faces toward the first side surface of the main body;
each of the plurality of layer portions further includes;
an insulating portion covering the first side surface of the semiconductor chip; and
a plurality of electrodes connected to the semiconductor chip;
the insulating portion has an end face located at the first side surface of the main body;
each of the plurality of electrodes has an end face located at the first side surface of the main body and surrounded by the insulating portion;
the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions; and
an entirety of the first side surface of the main body on which the wiring is disposed is flat without the wiring.
0 Assignments
0 Petitions
Accused Products
Abstract
A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.
50 Citations
3 Claims
-
1. A layered chip package comprising:
-
a main body having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; and a wiring disposed on the first side surface of the main body, wherein; the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes a semiconductor chip having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; the second, third and fourth side surfaces of the semiconductor chip are respectively located at the second, third and fourth side surfaces of the main body; the first side surface of the semiconductor chip faces toward the first side surface of the main body; each of the plurality of layer portions further includes;
an insulating portion covering the first side surface of the semiconductor chip; and
a plurality of electrodes connected to the semiconductor chip;the insulating portion has an end face located at the first side surface of the main body; each of the plurality of electrodes has an end face located at the first side surface of the main body and surrounded by the insulating portion; the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions; and an entirety of the first side surface of the main body on which the wiring is disposed is flat without the wiring.
-
-
2. A layered chip package comprising:
-
a main body having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; a first wiring disposed on the first side surface of the main body; and a second wiring disposed on the second side surface of the main body, wherein; the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes a semiconductor chip having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; the third and fourth side surfaces of the semiconductor chip are respectively located at the third and fourth side surfaces of the main body; the first and second side surfaces of the semiconductor chip respectively face toward the first and second side surfaces of the main body; each of the plurality of layer portions further includes;
an insulating portion covering the first and second side surfaces of the semiconductor chip; and
a plurality of first electrodes and a plurality of second electrodes connected to the semiconductor chip;the insulating portion has a first end face located at the first side surface of the main body, and a second end face located at the second side surface of the main body; each of the plurality of first electrodes has an end face located at the first side surface of the main body and surrounded by the insulating portion; each of the plurality of second electrodes has an end face located at the second side surface of the main body and surrounded by the insulating portion; the first wiring is connected to the end faces of the plurality of first electrodes of the plurality of layer portions; the second wiring is connected to the end faces of the plurality of second electrodes of the plurality of layer portions; and an entirety of the first side surface of the main body on which the first wiring is disposed and an entirety of the second side surface of the main body on which the second wiring is disposed are flat without the first and second wiring.
-
-
3. A layered chip package substructure for use for manufacturing a layered chip package, the layered chip package comprising:
-
a main body having a top surface, a bottom surface and four side surfaces; and a wiring disposed on at least one of the side surfaces of the main body, wherein; the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes; a semiconductor chip having a top surface, a bottom surface and four side surfaces, an insulating portion covering at least one of the four side surfaces of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip; the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed; each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, an entirety of the at least one side surface of the main body on which the wiring is disposed being flat without the wiring, the layered chip package substructure corresponding to one of the plurality of layer portions of the layered chip package, including a plurality of its corresponding layer portions, and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions, the layered chip package substructure comprising a substructure main body fabricated by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the substructure main body including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device, wherein; the substructure main body has a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer, and has at least one groove that opens at the first surface of the substructure main body and that extends to be adjacent to at least one of the pre-semiconductor-chip portions; and the at least one groove has a bottom that does not reach the second surface of the substructure main body, the layered chip package substructure further comprising; an insulating layer that fills the at least one groove and that will later become part of the insulating portion; and the plurality of electrodes each having a portion lying on the insulating layer.
-
Specification