Systems and methods for minimizing static leakage of an integrated circuit

• US 8,134,406 B2
• Filed: 06/13/2011
• Issued: 03/13/2012
• Est. Priority Date: 07/09/2004
• Status: Expired

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Caplan, Randy J., Schwake, Steven J.
• Primary Examiner(s): Zweizig, Jeffrey
• Application Number:
  US13/158,862
• Publication Number:
  US 20120001684A1
• Time in Patent Office: 274 Days
• Field of Search: 327/534, 327/535, 327/536, 327/537, 327/544
• US Class Current: 327/544
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

Claims

1. An integrated circuit comprising:

a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;

a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and

controller circuitry configured to;

i) monitor drain-source current of the sleep transistor;

ii) make a determination of whether to adjust the negative voltage in connection with adequate minimization of a static leakage of the integrated circuit; and

iii) adjust the negative voltage depending on the determination.

2. The integrated circuit of claim 1 wherein the controller circuitry is configured to continuously make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage.

3. The integrated circuit of claim 1 wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage.

4. The integrated circuit of claim 1 wherein the voltage generator is configured to selectively generate the negative voltage.

5. The integrated circuit of claim 1 wherein the voltage generator is a charge pump.

6. An integrated circuit comprising:

a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;

a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and

controller circuitry configured to;

i) monitor a drain-source current and a drain-gate current of either the sleep transistor or an emulated sleep transistor;

ii) make a determination of whether to adjust the negative voltage in connection with adequate minimization of a static leakage of the integrated circuit; and

iii) adjust the negative voltage depending on the determination.

7. The integrated circuit of claim 6 wherein the controller circuitry is configured to continuously make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage.

8. The integrated circuit of claim 6 wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage.

9. The integrated circuit of claim 6 wherein the voltage generator is configured to selectively generate the negative voltage.

10. The integrated circuit of claim 6 wherein the voltage generator is a charge pump.

11. An integrated circuit comprising:

a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;

a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and

controller circuitry configured to;

i) induce a current through an emulated sleep transistor in proportion to a static leakage of the integrated circuit;

ii) make a determination of whether to adjust the negative voltage depending on the amount of the current; and

iii) adjust the negative voltage depending on the determination.

12. The integrated circuit of claim 11 wherein the controller circuitry is configured to continuously make determinations of whether to adjust the negative voltage.

13. The integrated circuit of claim 11 wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage.

14. The integrated circuit of claim 11 wherein the voltage generator is configured to selectively generate the negative voltage.

15. The integrated circuit of claim 11 wherein the voltage generator is a charge pump.

16. An integrated circuit comprising:

a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;

a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and

a controller configured to receive the negative voltage and determine whether to adjust the negative voltage based on a comparison of a first current and a second current, the controller including;

i) a first transistor configured to receive the negative voltage that defines the first current through the first transistor;

ii) a second transistor configured to receive the negative voltage plus an offset voltage that define the second current through the second transistor; and

iii) circuitry configured to compare the first current to the second current.

17. The integrated circuit of claim 16 wherein the first and second transistors are emulated sleep transistors.

18. The integrated circuit of claim 17 wherein the voltage generator is configured to selectively generate the negative voltage.

19. The integrated circuit of claim 16 wherein the controller is configured to continuously determine whether to adjust the negative voltage.

20. The integrated circuit of claim 16 wherein the controller is configured to periodically determine whether to adjust the negative voltage.

21. The integrated circuit of claim 16 wherein the voltage generator is configured to selectively generate the negative voltage.

22. The integrated circuit of claim 21 wherein the voltage generator is a charge pump.

23. The integrated circuit of claim 16 wherein the voltage generator is a charge pump.