Varactor circuit and voltage-controlled oscillation

• US 8,134,418 B2
• Filed: 04/13/2010
• Issued: 03/13/2012
• Est. Priority Date: 04/13/2010
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Jiang, Xuewen
• Primary Examiner(s): Gannon, Levi
• Application Number:
  US12/759,658
• Publication Number:
  US 20110248787A1
• Time in Patent Office: 700 Days
• Field of Search: 331/36.C, 331/117.FE, 331/117.R, 331/167, 331/177.V
• US Class Current: 331/177.V
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only

Abstract

A varactor circuit and voltage-controlled oscillation are described. The varactor circuit includes a first varactor, a second varactor, a third varactor, and a fourth varactor. A first source-drain node of the first varactor and a second source-drain node of the second varactor are coupled to a first input node. A first gate node for the first varactor is coupled to a first output node. A second gate node for the second varactor is coupled to a second output node. A third gate node for the third varactor and a fourth gate node for the fourth varactor are coupled to a second input node. A third source-drain node of the third varactor is coupled to the first output node. A fourth source-drain node of the fourth varactor is coupled to the second output node. In other embodiments, varactor circuits block and re-center VCO output CML.

Claims

1. A varactor circuit, comprising:

a first varactor, a second varactor, a third varactor, and a fourth varactor;

wherein a first source-drain node of the first varactor is coupled to a first input node;

a second source-drain node of the second varactor is coupled to the first input node;

a first gate node of the first varactor is coupled to a first output node;

a second gate node of the second varactor is coupled to a second output node;

a third gate node of the third varactor is coupled to a second input node;

a fourth gate node of the fourth varactor is coupled to the second input node;

a third source-drain node of the third varactor is coupled to the first output node;

a fourth source-drain node of the fourth varactor is coupled to the second output node;

a resistance bridge coupled to the first gate node, the second gate node, the third source-drain node, and the fourth source-drain node;

the resistance bridge including at least one common mode voltage node; and

capacitors coupled for DC decoupling of a common mode voltage at the at least one common mode voltage node from a first sinusoidal voltage and a second sinusoidal voltage respectively at the first output node and the second output node;

wherein the resistance bridge includes;

a first resistor and a second resistor coupled to one another between the first gate node and the third source-drain node;

a third resistor and a fourth resistor coupled to one another between the second gate node and the fourth source-drain node;

the first resistor, the second resistor, the third resistor, and the fourth resistor connected to one another at the at least one common mode voltage node to couple the common mode voltage to each of the first gate node, the second gate node, the third source-drain node, and the fourth source-drain node; and

wherein the capacitors include;

a first capacitor coupled between the first output node and the first gate node;

a second capacitor coupled between the second output node and the second gate node;

a third capacitor coupled between the first output node and the third source-drain node; and

a fourth capacitor coupled between the second output node and the fourth source-drain node.

2. The varactor circuit according to claim 1, wherein the first varactor, the second varactor, the third varactor, and the fourth varactor are accumulation-mode MOS capacitors.

3. The varactor circuit according to claim 2, wherein:

the first input node and the second input node are respectively for receiving a first control voltage and a second control voltage for differential input; and

the first output node and the second output node are respectively for providing a first output voltage and a second output voltage.

4. The varactor circuit according to claim 3, wherein:

the first output voltage and the second output voltage are sinusoidal voltages;

the first control voltage and the second control voltage are DC voltages; and

the first output voltage and the second output voltage are at least approximately 180 degrees out of phase with respect to one another.

5. The varactor circuit according to claim 2, wherein the accumulation-mode MOS capacitors each have an n-type source region and an n-type drain region connected to one another for respectively providing the first source-drain node, the second source-drain node, the third source-drain node, and the fourth source-drain node.

6. The varactor circuit according to claim 5, wherein the n-type source region and the n-type drain region of each of the first varactor, the second varactor, the third varactor, and the fourth varactor are in an n-type well that provides a body region for each of the first varactor, the second varactor, the third varactor, and the fourth varactor.

7. The varactor circuit according to claim 1, wherein:

the first resistor and the third resistor are connected to one another between the first gate node and the second gate node at a first common mode voltage node of the at least one common mode voltage node;

the second resistor and the fourth resistor are connected to one another between the third source-drain node and the fourth source-drain node at a second common mode voltage node of the at least one common mode voltage node; and

the first resistor and the third resistor are coupled to the second resistor and the fourth resistor via a control circuit connected to the first common mode voltage node and the second common mode voltage node.

8. A voltage-controlled oscillator, comprising:

a varactor circuit coupled in parallel with an inductor circuit at a first output node and a second output node;

a first pair of cross-coupled transistors coupled to the varactor circuit and the inductor circuit at the first output node and the second output node;

a bias transistor coupled between the first pair of cross-coupled transistors and ground; and

a gate of the bias transistor coupled for receiving a bias voltage;

wherein the varactor circuit includes;

a first varactor, a second varactor, a third varactor, and a fourth varactor;

a first source-drain node of the first varactor and a second source-drain node of the second varactor are coupled to a first input node;

a first gate node of the first varactor is coupled to the first output node;

a second gate node of the second varactor is coupled to the second output node;

a third gate node of the third varactor and a fourth gate node of the fourth varactor are coupled to a second input node;

a third source-drain node of the third varactor is coupled to the first output node;

a fourth source-drain node of the fourth varactor is coupled to the second output node; and

a resistance bridge coupled to the first gate node, the second gate node, the third source-drain node, and the fourth source-drain node;

the resistance bridge including at least one common mode voltage node, and capacitors coupled for DC decoupling of a common mode voltage at the at least one common mode voltage node from a first sinusoidal voltage and a second sinusoidal voltage respectively at the first output node and the second output node;

wherein the resistance bridge includes;

a first resistor and a second resistor coupled to one another between the first gate node and the second gate node at a first common mode voltage node of the at least one common mode voltage node;

a third resistor and a fourth resistor coupled to one another between the third source-drain node and the fourth source-drain node at a second common mode voltage node of the at least one common mode voltage node; and

wherein the capacitors include;

a first capacitor coupled between the first output node and the first gate node;

a second capacitor coupled between the second output node and the second gate node;

a third capacitor coupled between the first output node and the third source-drain node; and

a fourth capacitor coupled between the second output node and the fourth source-drain node.

9. The voltage-controlled oscillator according to claim 8, wherein the first varactor, the second varactor, the third varactor, and the fourth varactor are accumulation-mode MOS capacitors.

10. The voltage-controlled oscillator according to claim 9, wherein:

the first input node and the second input node are respectively for receiving a first control voltage and a second control voltage for differential input; and

the first output node and the second output node are respectively for providing a first output voltage and a second output voltage.

11. The voltage-controlled oscillator according to claim 10, further comprising:

a second pair of cross-coupled transistors coupled to the varactor circuit and the inductor circuit at the first output node and the second output node; and

the second pair of cross-coupled transistors coupled to a supply voltage node.

12. The voltage-controlled oscillator according to claim 11, wherein:

the first pair of cross-coupled transistors are nMOS transistors;

the second pair of cross-coupled transistors are pMOS transistors;

a gate of a first nMOS transistor of the nMOS transistors and a drain of a second nMOS transistor of the nMOS transistors are connected to the first output node;

a gate of the second nMOS transistor and a drain of the first nMOS transistor are connected to the second output node;

a gate of a first pMOS transistor of the pMOS transistors and a drain of a second pMOS transistor of the pMOS transistors are connected to the first output node;

a gate of the second pMOS transistor and a drain of the first pMOS transistor are connected to the second output node;

a source of each of the first nMOS transistor and the second nMOS transistor are connected to a drain of the bias transistor; and

a source of each of the first pMOS transistor and the second pMOS transistor are connected to the supply voltage node coupled to receive a supply voltage.

13. The voltage-controlled oscillator according to claim 8, wherein:

the first resistor and the second resistor are coupled to the third resistor and the fourth resistor via a control circuit connected to the first common mode voltage node and the second common mode voltage node.

14. The voltage-controlled oscillator according to claim 13, wherein a supply voltage is provided via a PLL voltage contact of an integrated circuit die in which the varactor circuit is formed.

15. A method for providing a programmable voltage-controlled oscillation, comprising:

providing a first control voltage to a first pair of varactors;

providing a second control voltage to a second pair of varactors;

wherein the first control voltage has a first voltage range;

wherein the second control voltage has a second voltage range;

wherein the first voltage range and the second voltage range are associated with a gate-to-source voltage range of high capacitive gain range;

wherein the first control voltage and the second control voltage in combination provide a differential input;

operating the first pair of varactors in a first mode;

operating the second pair of varactors in a second mode;

wherein the first mode and the second mode are complementary modes;

wherein the differential input in combination with the complementary modes provides the high capacitive gain range associated with operation of the first pair of varactors and the second pair of varactors in combination;

providing a resistance bridge coupled to a first varactor and a second varactor of the first pair of varactors, and to a third varactor and a fourth varactor of the second pair of varactors;

the resistance bridge including at least one common mode voltage node, and capacitors coupled for DC decoupling of a common mode voltage at the at least one common mode voltage node from a first sinusoidal output voltage and a second sinusoidal output voltage respectively at a first output node and a second output node;

wherein the resistance bridge includes;

a first resistor and a second resistor coupled to one another between the first varactor and the third varactor;

a third resistor and a fourth resistor coupled to one another between the second varactor and the fourth varactor;

the first resistor, the second resistor, the third resistor, and the fourth resistor coupled to one another at the at least one common mode voltage node to couple the common mode voltage to each of the first varactor, the second varactor, the third varactor, and the fourth varactor; and

wherein the capacitors include;

a first capacitor coupled between the first output node and the first varactor;

a second capacitor coupled between the second output node and the second varactor;

a third capacitor coupled between the first output node and the third varactor; and

a fourth capacitor coupled between the second output node and the fourth varactor; and

outputting the first sinusoidal output voltage and the second sinusoidal output voltage having a frequency programmed responsive to the differential input and having a programmable frequency range responsive to the high capacitive gain range.

16. The method according to claim 15, further comprising:

providing the common mode voltage to the resistance bridge coupled to the first pair of varactors and the second pair of varactors;

setting voltage of the common mode voltage to move the high capacitive gain range into the gate-to-source voltage range responsive to semiconductor process variation; and

DC voltage isolating the common mode voltage for AC coupling of the first sinusoidal output voltage and the second sinusoidal output voltage for the outputting.

17. The method according to claim 16, wherein:

the providing of the common mode voltage to the resistance bridge includes;

apportioning a supply voltage to provide a first common mode voltage portion and a second common mode voltage portion; and

selectively providing the first common mode voltage portion and the second common mode voltage portion as the common mode voltage to respective common mode voltage nodes of the resistance bridge respectively coupled to the first pair of varactors and the second pair of varactors for re-centering common mode level associated with the common mode voltage.

18. The method according to claim 15, wherein:

the first resistor and the second resistor are coupled to the third resistor and the fourth resistor via a control circuit connected to the first common mode voltage node and the second common mode voltage node.

19. The method according to claim 18, wherein:

the control circuit has an adjustable resistance voltage divider coupled between a supply voltage node and ground; and

the control circuit further has a switch circuitry for selectively coupling;

a first divided voltage of a first voltage divider node of the voltage divider to the first common mode voltage node and a second voltage of a second voltage divider node of the voltage divider to the second common mode voltage node; and

the first divided voltage of the first voltage divider node of the voltage divider to the second common mode voltage node and the second voltage of the second voltage divider node of the voltage divider to the first common mode voltage node.