Integrated memory management and memory management method

• US 8,135,900 B2
• Filed: 09/24/2008
• Issued: 03/13/2012
• Est. Priority Date: 03/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kunimatsu, Atsushi, Nakai, Hiroto, Sakamoto, Hiroyuki, Maeda, Kenichi
• Primary Examiner(s): Lane, John
• Application Number:
  US12/236,880
• Publication Number:
  US 20090083478A1
• Time in Patent Office: 1,266 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Claims

1. A memory management device connectable to a non-volatile main memory and a processor comprising:

an acquiring unit acquiring logical addresses from the processor;

an address conversion unit converting logical addresses acquired by the acquiring unit into physical addresses of the non-volatile main memory; and

an access unit reading data from memory areas of the non-volatile main memory designated by physical addresses at reading, and writing data to memory areas of the non-volatile main memory designated by physical addresses at writing,

wherein the non-volatile main memory includes at least two regions, and the access unit determines which region to write writing data based on access frequency information associated with the writing data.

2. A device according to claim 1,

wherein the access frequency information of the writing data is determined based on whether the writing data is a part of compressed image data.

3. A device according to claim 2,

wherein one region of the non-volatile main memory is SLC (Single Level Cell) type memory, and another region of the non-volatile main memory is MLC (Multi Level Cell) type memory, and access unit writes the writing data to MLC area when the writing data is determined as the part of compressed image data.

4. A device according to claim 3,

wherein the access unit preloads preloading data from the non-volatile main memory based on the access frequency information.

5. A device according to claim 4,

wherein the non-volatile main memory is a NAND type flash main memory.

6. A device according to claim 1,

wherein the non-volatile main memory comprises a plurality of areas, each area having a group attribute, and

the address conversion unit determines physical address of the non-volatile main memory for the writing data based on the group attribute and the access frequency information associated with the writing data, the access frequency information being determined by an operating of a file management program on the processor.

7. A device according to claim 6,

wherein the access frequency information is determined based on whether the writing data is a part of compressed image data.

8. A memory unit comprising;

a plurality of non-volatile memory units formed on a substrate, wherein the non-volatile memory units are a main memory of the processor; and

a memory management unit formed on the substrate and connected to the non-volatile memory units, and connectable to a processor, comprising,

an acquiring unit acquiring logical addresses from the processor;

an address conversion unit converting logical addresses acquired by the acquiring unit into physical addresses of the non-volatile memory units; and

an access unit reading data from memory areas of the non-volatile memory units designated by physical addresses at reading, and writing data to memory areas of the non-volatile memory units designated by physical addresses at writing, wherein each non-volatile memory unit includes at least two regions and the access unit determines which region to write writing data based on access frequency information associated with the writing data and the memory management unit includes an RAID function for the non-volatile memory units, and a swap target non-volatile memory unit is able to swap when another non-volatile memory unit is operating.

9. A memory unit according to claim 8,

wherein the access frequency information of the writing data is determined based on whether the writing data is a part of compressed image data.

10. A memory management method comprising:

acquiring logical addresses from a processor;

converting logical addresses into physical addresses of a non-volatile main memory; and

reading data from memory areas of the non-volatile main memory designated by physical addresses, or writing data to memory areas of the non-volatile main memory designated by physical addresses,

wherein when writing data, determine which regions of the non-volatile main memory to write writing data based on access frequency information associated with the writing data.

11. A method according to claim 10,

wherein the access frequency information of the writing data is determined based on whether the writing data is a part of compressed image data.

12. A method according to claim 11,

wherein one region of the non-volatile main memory is SLC (Single Level Cell) type memory, and another region of the non-volatile main memory is MLC (Multi Level Cell) type memory, and writing the writing data to MLC area when the writing data is determined as the part of compressed image data.

13. A method according to claim 12, further comprising:

preloading data from non-volatile main memory based on the access frequency information.

14. A method according to claim 10,

wherein the non-volatile main memory comprises a plurality of areas, each area having group attribute, and determining physical address of the non-volatile main memory for the writing data based on the group attribute and the access frequency information associated with the writing data, the access frequency information being determined by an operating of a file management program on the processor.