Mixed multi-level cell and single level cell storage device

• US 8,135,913 B1
• Filed: 05/23/2011
• Issued: 03/13/2012
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sheredy, Joseph, Nguyen, Lau
• Primary Examiner(s): Lam, David
• Application Number:
  US13/113,236
• Time in Patent Office: 295 Days
• Field of Search: 711/118, 711112-114, 711/103, 711132-136
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write—erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write—erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Claims

1. A cache system configured to be operatively coupled to a memory module comprising a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the cache system comprising:

a memory cache; and

a cache controller configured to;

update, one or more times, one or more information units stored in the memory module;

track a frequency of updating of individual information units;

categorize individual information units based on the tracked frequency of updating; and

determine, for each information unit, whether the information unit is to be written to an SLC memory block or to an MLC memory block based at least in part on the categorizing.

2. The cache system of claim 1, wherein the cache controller is further configured to

categorize individual information units as either frequently updated information unit or infrequently updated information unit.

3. The cache system of claim 2, wherein the cache controller is further configured to

determine that an information unit is to be written to an SLC memory block based on categorizing the information unit as a frequently updated information unit.

4. The cache system of claim 2, wherein the cache controller is further configured to

determine that an information unit is to be written to an MLC memory block based on categorizing the information unit as infrequently updated information unit.

5. The cache system of claim 2, wherein the cache controller is further configured to

if a particular information unit is categorized as infrequently updated and is stored in an SLC block, instruct the memory module to store the particular information unit in an MLC block.

6. The cache system of claim 5, wherein the cache controller is further configured to

if the particular information unit is to be updated, update the particular information unit by forwarding the updated particular information unit to the memory module and instructing the memory module to write the updated particular information unit to an MLC block, and

instruct the memory module to erase the SLC block.

7. The cache system of claim 2, wherein the cache controller is further configured to

if a particular information unit is categorized as frequently updated and is stored in an MLC block, instruct the memory module to store the particular information unit in an SLC block.

8. The cache system of claim 7, wherein the cache controller is further configured to

if the particular information unit is to be updated, update the particular information unit by forwarding the updated particular information unit to the memory module and instructing the memory module to write the updated particular information unit to an SLC block, and

instruct the memory module to erase the MLC block.

9. The cache system of claim 1, wherein the cache controller is further configured to

categorize a first information unit as a frequently updated information unit if the first information unit is updated more than a threshold number of times during a given period of clock cycles, and

categorize a second information unit as an infrequently updated information unit if the information unit is updated less than a threshold number of times during the given period of clock cycles.

10. The cache system of claim 1, further comprising a frequency table, wherein the cache controller is further configured to adaptively update the frequency table with the tracked frequency of updating of individual information units.

11. A method of storing, using a cache controller within a cache system, individual information units in a memory module comprising a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising:

updating, one or more times, one or more information units stored in the memory module;

tracking a frequency of updating of individual information units;

categorizing individual information units based on the tracked frequency of updating; and

determining for each information unit, whether the information unit is to be written to an SLC memory block or to an MLC memory block based at least in part on the categorizing.

12. The method of claim 11, further comprising

categorizing individual information units as either frequently updated information unit or infrequently updated information unit.

13. The method of claim 12, further comprising

determining that an information unit is to be written to an SLC memory block based on the categorizing the information unit as a frequently updated information unit.

14. The method of claim 12, further comprising

determining that an information unit is to be written to an MLC memory block based on the categorizing the information unit as infrequently updated information unit.

15. The method of claim 12, further comprising

if a particular information unit is categorized as infrequently updated and is stored in an SLC block, instructing the memory module to store the particular information unit in an MLC block.

16. The method of claim 15, further comprising

if the particular information unit is to be updated, updating the particular information unit by forwarding the updated particular information unit to the memory module and instructing the memory module to write the updated particular information unit to an MLC block, and

instructing the memory module to erase the SLC block.

17. The method of claim 12, further comprising

if a particular information unit is categorized as frequently updated and is stored in an MLC block, instructing the memory module to store the particular information unit in an SLC block.

18. The method of claim 17, further comprising

if the particular information unit is to be updated, updating the particular information unit by forwarding the updated particular information unit to the memory module and instructing the memory module to write the updated particular information unit to an SLC block, and

instructing the memory module to erase the MLC block.

19. The method of claim 11, further comprising

categorizing a first information unit as a frequently updated information unit if the first information unit is updated more than a threshold number of times during a given period of clock cycles, and

categorizing a second information unit as an infrequently updated information unit if the information unit is updated less than a threshold number of times during the given period of clock cycles.