Multiprocessor electronic circuit including a plurality of processors and electronic data processing system

• US 8,135,960 B2
• Filed: 10/09/2008
• Issued: 03/13/2012
• Est. Priority Date: 10/30/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Koehler, Thomas, Fuchs, Thomas, Mayer, Ulrich, Shum, Chung-Lung Kevin, Swaney, Scott Barnett
• Primary Examiner(s): Zand, Kambiz
• Assistant Examiner(s): MOHAMMADI, FAHIMEH M
• Application Number:
  US12/248,549
• Publication Number:
  US 20090113212A1
• Time in Patent Office: 1,251 Days
• Field of Search: 713154-156, 713168-171, 713/182, 726/1, 726/3, 726 11- 15, 726/36, 380249-250
• US Class Current: 713/189
• CPC Class Codes: G06F 21/72 in cryptographic circuits

Abstract

A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.

Claims

1. A multiprocessor electronic circuit comprising:

a plurality of processors;

a single cryptographic processing unit comprising a plurality of input/output buffer pairs storing source data issued from and target data to be transmitted to the plurality of processors and further comprising two cryptographic engines, a cipher engine and a hash engine, wherein an assignment of one of the two cryptographic engines to one of the plurality of processors is performed independently from an assignment of the other of the two cryptographic engines; and

control logic for connecting the cryptographic processing unit to the plurality of processors and for temporarily assigning one of the two cryptographic engines to one of the plurality of processors.

2. The multiprocessor electronic circuit according to claim 1, wherein the cryptographic processing unit performs a reset procedure independently of each of the plurality of processors.

3. The multiprocessor electronic circuit according to claim 1, further comprising an indicator latch including a readline connected to one of the plurality of processors, wherein the indicator latch allows the processor to determine whether one of the two cryptographic engines is currently assigned to another of the plurality of processors.

4. The multiprocessor electronic circuit according to claim 1, further comprising control logic for performing at least one of:

a functional reset of the cryptographic processing unit or one of the two cryptographic engines,

error reporting,

a recovery/retry mechanism,

error reporting and handling for errors occurring during a transition of assignment of one of the two cryptographic engines, and

error reporting handling due to a power save status of the cryptographic processing unit.

5. An electronic data processing system comprising a multiprocessor electronic circuit, the multiprocessor electronic circuit comprising:

a plurality of processors;

a single cryptographic processing unit comprising a plurality of input/output buffer pairs storing source data issued from and target data to be transmitted to the plurality of processors and further comprising two cryptographic engines, a cipher engine and a hash engine, wherein an assignment of one of the two cryptographic engines to one of the plurality of processors is performed independently from an assignment of the other of the two cryptographic engines the; and

control logic for connecting the cryptographic processing unit to the plurality of processors and for temporarily assigning one of the two cryptographic engines to one of the plurality of processors.

6. The electronic data processing system according to claim 5, wherein the cryptographic processing unit performs a reset procedure independently of each of the plurality of processors.

7. The electronic data processing system according to claim 5, wherein the multiprocessor electronic circuit further comprises an indicator latch including a readline connected to one of the plurality of processors, wherein the indicator latch allows the processor to determine whether one of the two cryptographic engines is currently assigned to another of the plurality of processors.

8. The electronic data processing system according to claim 5, wherein the multiprocessor electronic circuit further comprises control logic for performing at least one of:

a functional reset of the cryptographic processing unit or one of the two cryptographic engines,

error reporting,

a recovery/retry mechanism,

error reporting and handling for errors occurring during a transition of assignment of one of the two cryptographic engines, and

error reporting handling due to a power save status of the cryptographic processing unit.