Three dimensional integrated circuits and methods of fabrication

• US 8,136,071 B2
• Filed: 09/12/2008
• Issued: 03/13/2012
• Est. Priority Date: 09/12/2007
• Status: Expired due to Fees

• Current Assignee: Neal Solomon
• Original Assignee: Neal Solomon
• Inventors: Solomon, Neal
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US12/283,443
• Publication Number:
  US 20090070727A1
• Time in Patent Office: 1,278 Days
• Field of Search: 716/9, 716/10, 716/13, 716/14, 326/38, 326/41, 326/47, 326/101, 257/211, 257/499, 257/798
• US Class Current: 716/119
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention relates to multi-planar logic components in a three-dimensional (3D) integrated circuit (IC) apparatus configuration. A multi-planar integrated circuit connected by through silicon vias is configured to connect microprocessor, FPGA and memory components. The integrated circuit components may be on tiles of layers of the 3D IC.

Claims

1. A three dimensional (3D) integrated circuit (IC) which is formed by organizing semiconductor integrated circuits into a multi-layer IC with through silicon vias (TSVs), comprising:

logic or memory circuits configured on circuit layers;

TSVs, connecting adjacent circuit layers;

wherein two or more circuit layers of ICs are connected with contiguous TSVs;

wherein electronic signals are transmitted through the TSVs from an IC on one layer of the multi-layer IC to other circuit layers;

wherein each circuit layer of the multi-layer IC contains individual tiles on which are structured logic or memory circuits;

wherein when at least two tiles on a same circuit layer of the multi-layer IC are connected, the tiles are connected by interconnects; and

wherein the multi-layer IC performs specific computational tasks.

2. The three dimensional integrated circuit of claim 1:

wherein the tiles are configured in irregular patterns;

wherein the irregular patterns of tiles consist of different size tiles; and

wherein the TSVs are configured to connect circuit components on tiles between two or more circuit layers.

3. The three dimensional integrated circuit of claim 1:

wherein at least one logic circuit type on a circuit layer in the multi-layer IC consists of a microprocessor.

4. The three dimensional integrated circuit of claim 1:

wherein at least one logic circuit type on a circuit layer in the multi-layer IC consists of a complex programmable logic device.

5. The three dimensional integrated circuit of claim 1:

wherein at least one logic circuit type on a circuit layer in the multi-layer IC consists of an application specific integrated circuit.

6. The three dimensional integrated circuit of claim 1:

wherein the TSVs in the multi-layer IC are integrated using an inverted pyramid configuration that connects circuit layers of the three dimensional integrated circuit.

7. A three dimensional (3D) integrated circuit (IC) which is formed by organizing semiconductor integrated circuits into a set of layers of circuits with through silicon vias (TSVs), comprising:

a multi-layer integrated circuit comprising at least two circuit layers of integrated circuits in a multi-layer system on a chip (SoC) module;

interconnects and TSVs to connect circuit components;

wherein the multi-layer IC is a hybrid circuit fabric consisting of a set of logic circuit types including at least, two of microprocessor or FPGA logic circuit components and at least one memory circuit component on at least two circuit layers;

wherein the multi-layer integrated circuit contains at least one of FPGA, microprocessor or memory circuit components on tiles on specific circuit layers; and

wherein the at least one logic circuit components and memory circuit component are connected by interconnects and TSVs.

8. The three dimensional integrated circuit of claim 7:

wherein the tiles are configured in irregular patterns;

wherein the irregular patterns of tiles consist of different size tiles; and

wherein the TSVs are configured to connect the circuit components on tiles between two or more circuit livers.

9. A multi-planar integrated circuit (IC) system consisting of a plurality of circuit planes in a three dimensional (3D) system on a chip (SoC) connected with through silicon vias (TSVs) comprised of:

a plurality of circuit layers, each layer of which includes at least one of logic and memory circuit components;

TSVs connecting circuits on adjacent circuit layers;

an interface configured to provide access to the memory and logic circuit components;

wherein logic and memory circuits on two or more layers of the plurality of circuit layers are connected with contiguous TSVs;

wherein the multi-planar IC is a heterogeneous fabric consisting of at least two of microprocessor, FPGA, ASIC and memory circuit components on tiles on specific circuit layers;

wherein interconnection between the circuit components on tiles of a same circuit layer of the multi-planar integrated circuit are connected by interconnects;

wherein the at least one memory circuits are used by at least one microprocessor, FPGA or ASIC circuit components; and

wherein the memory circuits store data and instructions.

10. The multi-planar integrated circuit system of claim 9:

wherein the tiles are configured in irregular patterns;

wherein the irregular patterns of tiles consist of different size tiles; and

wherein the TSVs are configured to connect the circuit components on tiles between two or more circuit layers.

11. The multi-planar integrated circuit system of claim 9:

wherein the memory circuits are accessed by logic circuit components on circuit layers within the 3D SoC.

12. The multi-planar integrated circuit system of claim 9:

wherein when the system uses the at least one logic circuit Component on one circuit layer to store and access data or instructions in at least one memory circuit on at least one circuit layer of the 3D SoC, a sequence of processing data or instructions changes in different logic applications.

13. The multi-planar integrated circuit system of claim 9:

wherein data and instructions are transmitted through the TSVs from the circuits on one layer of the 3D SoC to circuits on other layers.

14. The multi-planar integrated circuit system of claim 9:

wherein data or instructions are transferred between logic circuit components on at least one circuit layer.

15. The multi-planar integrated circuit system of claim 9:

wherein when an FPGA reconfigures its logic circuit configuration, at least one other logic circuit in the 3D SoC continues to process data and instructions.

16. The multi-planar integrated circuit system of claim 9:

wherein at least two memory circuits on at least two circuit layers are accessed by at least one logic circuit component of the 3D SoC.

17. The multi-planar integrated circuit of claim 9:

wherein the configuration of the 3D SoC is application specific.

18. The multi-planar integrated circuit system of claim 9:

wherein data or instructions from at least one logic circuit component in the 3D SoC are accessed simultaneously by at least two logic circuit components on at least one circuit layer.

19. The multi-planar integrated circuit system of claim 9:

wherein the data or instructions in a logic circuit component of a circuit layer are processed by at least one logic circuit component on at least one other circuit layer.

20. The multi-planar integrated circuit system of claim 9:

wherein a memory circuit of at least one circuit layer is accessed by a logic circuit component of at least one other circuit layer.