Arranging through silicon vias in IC layout

• US 8,136,084 B2
• Filed: 09/09/2009
• Issued: 03/13/2012
• Est. Priority Date: 09/09/2009
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Lindgren, Peter J., Miles, Glen L., Sprogis, Edmund J., Stamper, Anthony K., Dean, Donald R. Jr.
• Primary Examiner(s): Do, Thuan
• Application Number:
  US12/555,981
• Publication Number:
  US 20110057319A1
• Time in Patent Office: 916 Days
• Field of Search: 716/111, 716/126, 716/132, 716/139
• US Class Current: 716/139
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate

Abstract

A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.

Claims

1. A method comprising:

identifying, using at least one computer device, linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs, the plurality of TSVs being linearly aligned with one another, wherein the portion includes an array of substantially uniform periodicity of through silicon via (TSV) sets, each of the TSV sets being arranged in a given direction, and the identifying including;

defining a TSV set evaluation rectangle about each TSV set, each TSV set evaluation rectangle having a pair of X edges and a pair of Y edges,

calculating a Y spacing between adjacent TSV evaluation rectangles and an X spacing between adjacent TSV evaluation rectangles, and

expanding each TSV evaluation rectangle edge, excepting at a chip edge, in at least one Y direction by half the Y spacing between adjacent TSV evaluation rectangles and in at least one X direction by half the X spacing between adjacent TSV evaluation rectangles; and

modifying, using the at least one computer device, at least the portion of the IC layout to reduce a number of the linearly aligned TSVs, the modifying including, in response to a Y edge of a selected, expanded TSV evaluation rectangle contacting a Y edge of an adjacent, expanded TSV evaluation rectangle or an X edge of the selected, expanded TSV evaluation rectangle contacting an X edge of an adjacent, expanded TSV evaluation rectangle, rotating the TSV set within the selected TSV evaluation rectangle to be non-aligned to the given direction.

2. The method of claim 1, further comprising repeating the identifying and the modifying on the array.

3. The method of claim 1, wherein the modifying further includes ensuring each individual TSV within a TSV set is on a predetermined grid for the IC layout regardless of position.

4. The method of claim 1, wherein all of the TSVs in each of the TSV sets in the IC layout initially extend in a single direction.

5. The method of claim 4, further comprising determining the constant dimension based on a grid size of the IC layout.

6. The method of claim 1, wherein the plurality of TSVs in the IC layout initially extend in a single direction.

7. A system comprising:

an identifier for identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs, the plurality of TSVs being linearly aligned with one another, wherein the portion includes an array of substantially uniform periodicity of through silicon via (TSV) sets, each of the TSV sets being arranged in a given direction, and wherein the identifier;

defines a TSV set evaluation rectangle about each TSV set, each TSV set evaluation rectangle having a pair of X edges and a pair of Y edges,

calculates a Y spacing between adjacent TSV evaluation rectangles and an X spacing between adjacent TSV evaluation rectangles, and

expands each TSV evaluation rectangle edge, excepting at a chip edge, in at least one Y direction by half the Y spacing between adjacent TSV evaluation rectangles and in at least one X direction by half the X spacing between adjacent TSV evaluation rectangles; and

a modifier for modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs, wherein the modifier, in response to a Y edge of a selected, expanded TSV evaluation rectangle contacting a Y edge of an adjacent, expanded TSV evaluation rectangle or an X edge of the selected, expanded TSV evaluation rectangle contacting an X edge of an adjacent, expanded TSV evaluation rectangle, rotates the TSV set within the selected TSV evaluation rectangle to be non-aligned to the given direction.

8. The system of claim 7, wherein the identifier and the modifier repeat the identifying and the modifying on the array.

9. The system of claim 7, wherein the modifier further ensures each individual TSV within a TSV set is on a predetermined grid for the IC layout regardless of position.

10. The system of claim 7, wherein all of the TSVs in the TSV sets in the IC layout initially extend in a single direction.

11. The system of claim 7, wherein the plurality of TSVs in the IC layout initially extend in a single direction.

12. The system of claim 7, wherein a constant dimension of the rectangle is based on a grid size of the IC layout.

13. A program product stored on a computer-readable storage device, which when executed, arranges through silicon vias, the program product comprising:

program code for identifying linearly aligned through silicon vias (TSVs) in a portion of an integrated circuit (IC) layout that includes a plurality of TSVs, the plurality of TSVs being linearly aligned with one another, wherein the portion includes an array of substantially uniform periodicity of through silicon via (TSV) sets, each of the TSV sets being arranged in a given direction, and the identifying program code includes program code for;

defining a TSV set evaluation rectangle about each TSV set, each TSV set evaluation rectangle having a pair of X edges and a pair of Y edges,

calculating a Y spacing between adjacent TSV evaluation rectangles and an X spacing between adjacent TSV evaluation rectangles, and

expanding each TSV evaluation rectangle edge, excepting at a chip edge, in at least one Y direction by half the Y spacing between adjacent TSV evaluation rectangles and in at least one X direction by half the X spacing between adjacent TSV evaluation rectangles; and

program code for modifying at least the portion of the IC layout to reduce a number of the linearly aligned TSVs, wherein the modifying program code includes program code for, in response to a Y edge of a selected, expanded TSV evaluation rectangle contacting a Y edge of an adjacent, expanded TSV evaluation rectangle or an X edge of the selected, expanded TSV evaluation rectangle contacting an X edge of an adjacent, expanded TSV evaluation rectangle, rotating the TSV set within the selected TSV evaluation rectangle to be non-aligned to the given direction.

14. The program product of claim 13, wherein the modifying program code further ensures each individual TSV within a TSV set is on a predetermined grid for the IC layout regardless of position.