Method of forming thin profile WLCSP with vertical interconnect over package footprint

• US 8,138,014 B2
• Filed: 01/29/2010
• Issued: 03/20/2012
• Est. Priority Date: 01/29/2010
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Chi, HeeJo, Cho, NamJu, Shin, HanGil
• Primary Examiner(s): NGUYEN, THANH T
• Application Number:
  US12/696,923
• Publication Number:
  US 20110186977A1
• Time in Patent Office: 781 Days
• Field of Search: 438106-114
• US Class Current: 438/106
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of first semiconductor die each with an active surface;

mounting a second semiconductor die to the first semiconductor die, the active surface of the first semiconductor die being oriented toward an active surface of the second semiconductor die;

depositing an encapsulant over the first and second semiconductor die;

removing a portion of a back surface of the second semiconductor die opposite the active surface;

forming conductive pillars around the second semiconductor die;

forming an interconnect structure over the back surface of the second semiconductor die, encapsulant, and conductive pillars, the interconnect structure being electrically connected to the conductive pillars;

removing a portion of a back surface of the first semiconductor die opposite the active surface; and

singulating the semiconductor wafer into individual semiconductor devices.

2. The method of claim 1, further including mounting a discrete semiconductor component to the first semiconductor die.

3. The method of claim 1, further including forming a conductive via through the first semiconductor die.

4. The method of claim 1, further including forming a heat sink over the back surface of the first semiconductor die.

5. The method of claim 1, further including forming a shielding layer over the back surface of the first semiconductor die.

6. The method of claim 1, further including mounting side-by-side semiconductor die over the first semiconductor die.

7. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of first semiconductor die each with an active surface;

mounting a second semiconductor die to the first semiconductor die, the active surface of the first semiconductor die being oriented toward an active surface of the second semiconductor die;

forming a vertical interconnect structure around the second semiconductor die;

depositing an encapsulant over the first and second semiconductor die;

removing a portion of a back surface of the second semiconductor die opposite the active surface;

forming a build-up interconnect structure over the back surface of the second semiconductor die, encapsulant, and vertical interconnect structure, the build-up interconnect structure being electrically connected to the vertical interconnect structure;

removing a portion of a back surface of the first semiconductor die opposite the active surface; and

singulating the semiconductor wafer into individual semiconductor devices.

8. The method of claim 7, further including mounting a discrete semiconductor component to the first semiconductor die.

9. The method of claim 7, further including forming a conductive via through the first semiconductor die.

10. The method of claim 7, further including forming a heat sink over the back surface of the first semiconductor die.

11. The method of claim 7, further including forming a shielding layer over the back surface of the first semiconductor die.

12. The method of claim 7, wherein the vertical interconnect structure includes a conductive pillar, stacked bumps, post and pillar, or bump and pillar.

13. The method of claim 7, wherein forming the vertical interconnect structure includes:

mounting a leadframe interposer over the first and second semiconductor die prior to depositing the encapsulant, the leadframe interposer including plate and bodies extending from the plate to the first semiconductor die;

depositing the encapsulant over the first and second semiconductor die and around the bodies of the leadframe interposer; and

removing the plate to leave the bodies in the encapsulant as conductive pillars around the second semiconductor die.

14. A method of manufacturing a semiconductor device, comprising:

providing a first semiconductor die having an active surface;

mounting a second semiconductor die to the first semiconductor die, the active surface of the first semiconductor die being oriented toward an active surface of the second semiconductor die;

forming a vertical interconnect structure around the second semiconductor die;

depositing an encapsulant over the first and second semiconductor die;

removing a portion of a back surface of the second semiconductor die opposite the active surface;

forming a build-up interconnect structure over the back surface of the second semiconductor die, encapsulant, and vertical interconnect structure, the build-up interconnect structure being electrically connected to the vertical interconnect structure; and

removing a portion of a back surface of the first semiconductor die opposite the active surface.

15. The method of claim 14, further including mounting a discrete semiconductor component to the first semiconductor die.

16. The method of claim 14, further including forming a conductive via through the first semiconductor die.

17. The method of claim 14, further including forming a heat sink over the back surface of the first semiconductor die.

18. The method of claim 14, further including forming a shielding layer over the back surface of the first semiconductor die.

19. The method of claim 14, wherein the vertical interconnect structure includes a conductive pillar, stacked bumps, post and pillar, or bump and pillar.

20. The method of claim 14, wherein forming the vertical interconnect structure includes:

mounting a leadframe interposer over the first and second semiconductor die prior to depositing the encapsulant, the leadframe interposer including plate and bodies extending from the plate to the first semiconductor die;

depositing the encapsulant over the first and second semiconductor die; and

removing the plate to leave the bodies in the encapsulant as conductive pillars around the second semiconductor die.