Method for manufacturing thin film transistor having microcrystalline semiconductor film

• US 8,138,032 B2
• Filed: 04/14/2009
• Issued: 03/20/2012
• Est. Priority Date: 04/18/2008
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyairi, Hidekazu, Dairiki, Koji, Egi, Yuji, Jinbo, Yasuhiro, Isa, Toshiyuki
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Valentine, Jami M
• Application Number:
  US12/423,111
• Publication Number:
  US 20100096631A1
• Time in Patent Office: 1,071 Days
• Field of Search: 257/58, 257/E21.414, 257/E29.273, 438/158
• US Class Current: 438/158
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which includes a plurality of crystalline regions in an amorphous structure and which forms a channel formation region, in contact with the gate insulating layer; a semiconductor layer including an impurity element imparting one conductivity type, which forms source and drain regions; and a buffer layer including an amorphous semiconductor between the semiconductor layer and the semiconductor layer including an impurity element imparting one conductivity type. The crystalline regions have an inverted conical or inverted pyramidal crystal particle which grows approximately radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer.

Claims

1. A method for manufacturing a thin film transistor comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode;

forming a semiconductor layer over the gate insulating layer in the presence of plasma;

forming a buffer layer over the semiconductor layer, the buffer layer comprising an amorphous semiconductor;

forming source and drain regions over the buffer layer, the source and drain regions including an impurity element; and

forming source and drain electrodes over the source and drain regions, respectively,

wherein the step of the formation of the semiconductor layer includes;

forming a first region using a semiconductor source gas and a gas containing nitrogen so that the first region has an amorphous structure; and

forming a second region over the first region using the semiconductor source gas in the absence of the gas containing nitrogen so that the second region has a crystal particle of a semiconductor.

2. The method for manufacturing a thin film transistor according to claim 1,

wherein the gate insulating layer includes nitrogen.

3. The method for manufacturing a thin film transistor according to claim 1,

wherein the gas containing nitrogen is selected from ammonia, nitrogen, nitrogen chloride, and nitrogen fluoride.

4. The method for manufacturing a thin film transistor according to claim 1,

wherein the semiconductor source gas is a silicon hydride gas, a silicon fluoride gas, or a silicon chloride gas.

5. The method for manufacturing a thin film transistor according to claim 1,

wherein the gate insulating layer comprises nitrogen.