Method and structure for gate height scaling with high-k/metal gate technology

• US 8,138,037 B2
• Filed: 03/02/2010
• Issued: 03/20/2012
• Est. Priority Date: 03/17/2009
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Chudzik, Michael P., Donaton, Ricardo A., Henson, William K., Liang, Yue
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US12/715,781
• Publication Number:
  US 20100237435A1
• Time in Patent Office: 749 Days
• Field of Search: 438/199, 438/210, 438/215, 438/281, 257/E21.632
• US Class Current: 438/199
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor;

selectively removing the dummy gate while protecting the at least one polysilicon feature; and

forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.

2. The method of claim 1, wherein the at least one polysilicon feature comprises a first polysilicon feature associated with a resistor and a second polysilicon feature associated with an e-fuse.

3. The method of claim 2, wherein:

the first polysilicon feature and the second polysilicon feature are formed over an isolation region of a substrate;

the dummy gate is formed over an active region of the substrate; and

the active region is adjacent to the isolation region.

4. The method of claim 1, further comprising:

forming a high-k dielectric layer on a substrate;

forming the gate metal layer on the high-k dielectric layer;

forming a silicon layer on the gate metal layer;

forming an etch-stop layer on the silicon layer; and

forming the polysilicon layer on the etch-stop layer.

5. The method of claim 4, further comprising:

forming a barrier layer on the substrate, over the dummy gate, and over the at least one polysilicon feature;

forming a dielectric layer on the barrier layer; and

removing a portion of the barrier layer over the dummy gate.

6. The method of claim 5, further comprising masking the barrier layer over the at least one polysilicon feature during the removing the portion of the barrier layer over the dummy gate.

7. The method of claim 5, further comprising removing the etch-stop layer after removing the dummy gate.

8. The method of claim 7, wherein:

the removing the etch-stop layer exposes the silicon layer; and

the forming the gate contact comprises forming a silicide using the silicon layer.

9. The method of claim 1, wherein:

the metal gate has a height of about 10 nm to about 30 nm; and

the at least one polysilicon feature has a height of about 50 nm to about 80 nm.

10. A method of forming a semiconductor device, comprising:

forming a high-k dielectric layer on a substrate;

forming a metal layer on the high-k dielectric layer;

forming a silicon layer on the metal layer;

forming an etch-stop layer on the silicon layer;

forming a polysilicon layer on the etch-stop layer;

patterning the polysilicon layer into a dummy gate associated with a transistor and at least one polysilicon feature associated with at least one other device;

forming a barrier layer over the substrate, the dummy gate, and the at least one polysilicon feature;

removing a portion of the barrier layer from over the dummy gate while masking the barrier layer over the at least one polysilicon feature;

selectively removing the dummy gate to expose a portion of the etch-stop layer;

removing the exposed portion of the etch-stop layer to expose a portion of the silicon layer; and

forming a silicide gate contact from the exposed silicon layer.

11. The method of claim 10, wherein a metal gate of the transistor comprising a portion of the metal layer and the silicide gate contact has a gate height that is less than half a height of the at least one polysilicon feature.

12. The method of claim 11, wherein:

the metal gate has a height of about 10 nm to about 30 nm; and

the at least one polysilicon feature has a height of about 50 nm to about 80 nm.

13. The method of claim 10, wherein the at least one polysilicon feature comprises a first polysilicon feature associated with a resistor and a second polysilicon feature associated with an e-fuse.

14. The method of claim 13, wherein:

the first polysilicon feature and the second polysilicon feature are formed over an isolation region of a substrate;

the dummy gate is formed over an active region of the substrate; and

the active region is adjacent to the isolation region.

15. The method of claim 13, further comprising forming a silicide contact on the second polysilicon feature.

16. The method of claim 10, wherein the removing the portion of the barrier layer from over the dummy gate exposes a silicide portion on the dummy gate, and further comprising removing the silicide portion prior to removing the dummy gate.