Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array

• US 8,138,039 B2
• Filed: 03/25/2011
• Issued: 03/20/2012
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Burke, Robert J., Srinivasan, Anand
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US13/071,628
• Publication Number:
  US 20110171796A1
• Time in Patent Office: 361 Days
• Field of Search: 438/253, 438/268, 438/209, 438/212, 438/396, 438/488, 257/E21.41, 257/E21.648
• US Class Current: 438/209
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.

Claims

1. A method of fabricating a vertical semiconductor transistor, said method comprises:

providing a semiconductor substrate;

forming a polysilicon pillar on the substrate;

using the thickness of a first film layer to define a first source/drain region of the transistor as the top portion of the pillar;

forming a spacer layer around the top portion of the pillar;

using the thickness of a second film layer to define a channel region of the transistor as the central portion of the pillar and to align a transistor gate with the channel region of the transistor;

depositing a dielectric layer on the pillar in alignment with the channel region of the transistor;

forming the transistor gate in alignment with the channel region of the transistor, wherein the transistor gate is formed to surround the pillar with the dielectric layer between a conductive material and the pillar;

using the thickness of the spacer layer around the top portion of the pillar to define the thickness of the transistor gate, a top portion of the transistor gate being underneath a bottom portion of the spacer layer; and

defining a second source/drain region of the transistor as the bottom portion of the pillar using the thickness of a third film layer.

2. The method according to claim 1, wherein the act of forming the transistor gate includes depositing a layer of conductive material to surround the pillar with the dielectric layer between the conductive material and the pillar, and further comprising the act of defining a conductive path as a portion of the conductive material layer extending from the transistor gate.

3. The method of claim 2, wherein the layer of conductive material is a metal layer.

4. The method of claim 2, wherein the layer of conductive material is a layer of polysilicon.

5. The method of claim 4, further comprising the step of doping the layer of polysilicon.

6. A method of fabricating a semiconductor structure containing at least one vertical transistor, the method comprising the acts of:

providing a substrate wherein at least a portion of the working surface thereof is polysilicon;

depositing first, second and third material layers on the substrate;

forming at least one hole through the material layers over the polysilicon portion of the substrate surface to thereby expose the polysilicon;

epitaxially growing a respective polysilicon pillar from the polysilicon portion of the substrate surface through each of the at least one hole;

forming a protective cap layer over each pillar;

removing the third material layer to thereby expose the sidewall surface of a top portion of each pillar;

forming a spacer layer around the top portion of each pillar on the exposed sidewall surface thereof;

removing the second material layer to thereby expose the sidewall surface of a central portion of each pillar, the central portion being adjacent and beneath the spacer layer;

depositing a dielectric layer around the central portion of each pillar on the exposed sidewall surface thereof; and

surrounding the dielectric layer of each pillar with a layer of conductive material.

7. The method of claim 6, wherein the top portion of each pillar forms a first source/drain region of a respective transistor, the central portion of each pillar forms a channel region of the respective transistor, the bottom portion of each pillar forms a second source/drain region of the respective transistor, and a region of the conductive material surrounding each pillar forms a transistor gate of the respective transistor.

8. The method of claim 6, wherein at least one of the material layers comprises an insulating material.

9. The method of claim 6, wherein each of the material layers comprises an insulating material.

10. The method of claim 6, wherein each of the material layers comprises an insulating layer, each insulating layer is separated from an adjacent insulating layer by a nitride liner.

11. The method of claim 6, further comprising the step of patterning the layer of conductive material to form a conductive path extending from the pillar.

12. A method of fabricating a semiconductor structure containing at least one vertical transistor, the method comprising the steps of:

providing a substrate having a silicon layer disposed over an insulator layer;

patterning the silicon layer to form M digit lines, wherein M is a positive integer;

depositing a plurality of material layers over the substrate;

forming an M×

N array of holes aligned over the M digit lines, wherein N is a positive integer and N holes are formed along each digit line and are aligned with the holes formed over adjacent digit lines;

epitaxially growing a respective polysilicon pillar from the polysilicon portion of the substrate surface through each hole;

forming a protective cap layer over each pillar;

exposing a sidewall surface of a top portion of each pillar;

forming a spacer layer around the top portion of each pillar on the exposed sidewall surface;

exposing the sidewall surface of a central portion of each pillar;

depositing a dielectric layer around the central portion of each pillar on the exposed sidewall surface; and

surrounding the dielectric layer of each pillar with a layer of conductive material.

13. The method of claim 12, wherein the top portion of each pillar forms a first source/drain region of a respective transistor, the central portion of each pillar forms a channel region of the respective transistor, the bottom portion of each pillar forms a second source/drain region of the respective transistor, and a region of the conductive material surrounding each pillar forms a transistor gate of the respective transistor.

14. The method of claim 12, wherein forming the M digit lines comprises:

patterning the silicon layer to remove a plurality of strips to provide alternating rows of raised and recessed surfaces on the substrate, the raised rows being defined by the remaining strips of the silicon layer, and the recessed rows being defined by the exposed surfaces of the insulator upon removing the plurality of strips of the polysilicon layer, and

depositing insulator material to fill in the recesses between the raised rows.

15. The method of claim 12, further comprising siliciding the silicon digit lines.

16. The method of claim 12, further comprising patterning the layer of conductive material to form N conductive paths.

17. The method of claim 12, further comprising:

removing the protective cap from each pillar to expose the top end of the respective pillar; and

constructing a capacitor over the top end of each pillar in the array, wherein a bottom plate of the capacitor is formed in direct contact with the top end of the pillar.

18. The method of claim 17, wherein the step of constructing the capacitor comprises forming a single-sided container capacitor.