Thin film transistor array substrate and method for manufacturing the same

• US 8,138,548 B2
• Filed: 07/16/2010
• Issued: 03/20/2012
• Est. Priority Date: 05/12/2010
• Status: Active Grant

• Current Assignee: E Ink Holdings Incorporated
• Original Assignee: E Ink Holdings Incorporated
• Inventors: Huang, Sung-Hui, Lan, Wei-Chou, Shinn, Ted-Hong
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US12/838,107
• Publication Number:
  US 20110278563A1
• Time in Patent Office: 613 Days
• Field of Search: 438/258, 438/285, 438/479, 438/483, 438/FOR.200, 257/347, 257/E29.296, 257/E21.411, 257/E21.46
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

A thin film transistor array substrate includes a substrate, a gate layer, a gate insulating layer, a source/drain layer, a patterned protective layer, an oxide semiconductor layer, a resin layer and a pixel electrode. The gate layer is disposed on the substrate. The gate insulating layer is disposed on the gate layer and the substrate. The source/drain layer is disposed on the gate insulating layer. The patterned protective layer is disposed on the source/drain layer and exposes a portion of the source/drain layer. The oxide semiconductor layer is disposed on the patterned protective layer and electrically connected to the source/drain layer. The resin layer is disposed on the oxide semiconductor layer and covers the oxide semiconductor layer. The pixel electrode is disposed on the resin layer and connects to the source/drain layer. The present invention also provides a method for making the thin film transistor array substrate. The thin film transistor array substrate can prevent leakage current.

Claims

1. A thin film transistor array substrate, comprising:

a substrate;

a gate layer, disposed on the substrate;

a gate insulating layer, disposed on the gate layer and the substrate;

a source/drain layer, disposed on the gate insulating layer;

a patterned protective layer, disposed on the source/drain layer and exposing a portion of the source/drain layer;

an oxide semiconductor layer, disposed on the patterned protective layer and electrically connected to the source/drain layer;

a resin layer, disposed on the oxide semiconductor layer to cover the oxide semiconductor layer; and

a pixel electrode, disposed on the resin layer and connected to the source/drain layer.

2. The thin film transistor array substrate of claim 1, wherein the oxide semiconductor layer is an amorphous oxide that comprises at least one of indium, gallium, zinc.

3. The thin film transistor array substrate of claim 1, wherein the oxide semiconductor layer comprises amorphous indium gallium zinc oxide.

4. The thin film transistor array substrate of claim 1, wherein the resin layer is positive or negative photo resist.

5. The thin film transistor array substrate of claim 1, wherein a portion of the pixel electrode is directly disposed on the patterned protective layer.

6. A method for manufacturing thin film transistor array substrate, comprising:

forming a gate layer on a substrate;

forming a gate insulating layer on the gate layer and the substrate;

forming a source/drain layer on the gate insulating layer;

forming a patterned protective layer on the source/drain layer to expose a portion of the source/drain layer;

forming an oxide semiconductor layer on the patterned protective layer, the oxide semiconductor layer being electrically connected to the source/drain layer;

forming a resin layer on the oxide semiconductor layer to cover the oxide semiconductor layer; and

forming a pixel electrode on the resin layer, the pixel electrode being connected to the source/drain layer.

7. The method for manufacturing the thin film transistor array substrate of claim 6, wherein the oxide semiconductor layer is an amorphous oxide that comprises at least one of indium, gallium, zinc.

8. The method for manufacturing the thin film transistor array substrate of claim 6, wherein the oxide semiconductor layer comprises amorphous indium gallium zinc oxide.

9. The method for manufacturing the thin film transistor array substrate of claim 6, wherein the resin layer is positive or negative photo resist.

10. The method for manufacturing the thin film transistor array substrate of claim 6, wherein during the formation of the oxide semiconductor layer, oxygen and argon gas are introduced.