PCM with poly-emitter BJT access devices

• US 8,138,574 B2
• Filed: 07/28/2009
• Issued: 03/20/2012
• Est. Priority Date: 05/16/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Tze-Chiang, Lam, Chung Hon, Rajendran, Bipin
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Rodela, Eduardo A
• Application Number:
  US12/510,588
• Publication Number:
  US 20110024712A1
• Time in Patent Office: 966 Days
• Field of Search: 257/1, 257/2, 257/5, 257/205, 257/477, 257/536, 257/539, 257/E27.019, 257/E27.021, 257/E27.03, 257/E27.032, 365/148
• US Class Current: 257/539
• CPC Class Codes: H10B 63/32 of the bipolar type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.

Claims

1. A phase change memory (PCM) comprising:

an array comprising a plurality of memory cells, a memory cell comprising;

a phase change element (PCE); and

a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor;

wherein a cross-section of an emitter region of the BJT comprises a square having an area and a side length, and wherein an area of a memory cell of the plurality of memory cells is 5 or 6 times the area of the cross-section of the emitter region of the BJT.

2. The PCM of claim 1, wherein the array comprises a plurality of parallel semiconductor regions separated by a plurality of shallow trench isolation regions, and wherein the plurality of memory cells are located in the plurality of parallel semiconductor regions.

3. The PCM of claim 2, wherein the parallel semiconductor regions have a width that is approximately twice the side length of the cross-section of the emitter region of the BJT, and the shallow trench isolation regions have a width that is equal to the side length of the cross-section of the emitter region of the BJT.

4. The PCM of claim 2, wherein a plurality of memory cells are located in the middle of the parallel semiconductor regions such that a plurality of BJTs associated with the plurality of memory cells are separated from an edge of the shallow trench isolation regions by at least a distance of half of the side length of the cross-section of the emitter region of the BJT in all directions.

5. The PCM of claim 2, wherein the parallel semiconductor regions are of a width that is approximately 1.5 times the side length of the cross-section of the emitter region of the BJT, and the shallow trench isolation regions are of a width that is equal to the side length of the cross-section of the emitter region of the BJT.

6. The PCM of claim 2, wherein a plurality of memory cells are located in the parallel semiconductor regions such that a plurality of BJTs associated with the plurality of memory cells are adjacent to the shallow trench isolation region on a first side and are separated from an edge of the shallow trench isolation regions by at least a width of half of the side length of the cross-section of the emitter region of the BJT on a second side that is opposite the first side.

7. The PCM of claim 1, wherein the BJT comprises a sidewall spacer comprising silicon nitride.

8. A memory cell for a phase change memory (PCM), comprising:

a phase change element (PCE); and

a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor;

wherein a cross-section of an emitter region of the BJT comprises a square that has an area and a side length, and wherein an area of the memory cell is 5 or 6 times the area of the cross-section of the emitter region of the BJT.

9. The memory cell for a PCM of claim 8, wherein the BJT comprises a sidewall spacer comprising silicon nitride.

10. The memory cell for a PCM of claim 8, wherein the BJT is separated from a BJT in an adjacent memory cell by a distance that is approximately twice the side length of the cross-section of the emitter region of the BJT in a word line direction of the PCM, and by a distance that is three times the side length of the cross-section of the emitter region of the BJT in a bit line direction of the PCM.

11. The memory cell for a PCM of claim 8, wherein the BJT is separated from a BJT in an adjacent memory cell by a distance that is approximately twice the side length of the cross-section of the emitter region of the BJT in a word line direction of the PCM, and by a distance that is two and a half times the side length of the cross-section of the emitter region of the BJT in a bit line direction of the PCM.