Configuration context switcher with a clocked storage element

• US 8,138,789 B2
• Filed: 10/04/2010
• Issued: 03/20/2012
• Est. Priority Date: 09/06/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Chandler, Trevis, Entjer, Joe, Voogel, Martin, Redgrave, Jason
• Primary Examiner(s): Cho, James
• Application Number:
  US12/897,778
• Publication Number:
  US 20110018582A1
• Time in Patent Office: 533 Days
• Field of Search: 326 37- 41, 326/47
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17768 for security
• CPC Class Codes: H03K 3/0372 of the master-slave type

Abstract

Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

Claims

1. An integrated circuit (“

IC”

) comprising;

a configurable circuit for configurably performing one of a plurality of operations based on configuration data;

a plurality of configuration storage circuits for storing a plurality of configuration data sets for the configurable circuit; and

an interconnect circuit for switchably connecting the configurable circuit to different sets of the configuration storage circuits to receive different configuration data sets, said interconnect circuit comprising (i) a set of clocked storage circuits and (ii) a set of unclocked storage circuits for temporarily storing the received configuration data sets.

2. The IC of claim 1, wherein the set of clocked storage circuits is further for providing a received configuration data set to the configurable circuit after temporarily storing the received configuration data set.

3. The IC of claim 1, wherein the set of clocked storage circuits is further (i) for receiving different configuration data sets from different sets of configuration storage circuits at different instances in time and (ii) for temporarily storing each received particular configuration data set before providing the received particular configuration data set to the configurable circuit.

4. The IC of claim 3, wherein the set of unclocked storage circuits comprises a set of master storage circuits, wherein the set of clocked storage circuits comprises a set of slave storage circuits,

said set of master storage circuits for receiving different configuration data sets from different sets of configuration storage circuits at different instances in time, and for temporarily storing each received particular configuration data set before providing the received particular configuration data set to the set of slave storage circuits,

said set of slave storage circuits for receiving different configuration data sets from the set of master storage circuits at different instances in time, and for providing each received particular configuration data set to the configurable circuit.

5. The IC of claim 1, wherein at least one clocked storage circuit comprises a storage cell for storing configuration data, wherein the clocked storage circuit receives a clock signal that enables the storage cell to receive and store configuration data that the clocked storage circuit receives.

6. The IC of claim 5, wherein the clock signal has a first state and a second state, wherein during the first state, the clock signal enables the storage cell to receive configuration data that the clocked storage circuit receives, wherein during the second state, the storage cell stores the configuration data that the storage cell received while the clock was in the first state.

7. The IC of claim 5,

wherein the storage cell comprises cross coupled inverters that store data on two complementary storage nodes,

wherein the storage circuit cell further comprises override circuitry for temporarily overriding the cross coupled inverters to write data to the two complementary storage nodes,

wherein the override circuitry is disabled after data is written to the complementary storage nodes and the two cross coupled inverters maintain the data on the two complementary storage nodes.

8. The IC of claim 5, wherein the storage cell maintains the stored configuration data for a period of time even when an input to the clocked storage circuit changes.

9. The IC of claim 5, wherein the clock signal enables at least one transistor that connects the storage cell to a power source.

10. The IC of claim 9, wherein the power source is an electrical ground.

11. The IC of claim 1, wherein the interconnect circuit comprises a first stage and a second stage for transferring the configuration data from the configuration storage circuits to the configurable circuit, wherein the first stage receives the configuration data from a set of configuration storage circuits and the second stage holds the received configuration data in order to propagate the received configuration data to the configurable circuits, wherein the set of clocked storage circuits is in the second stage of the interconnect circuit.

12. The IC of claim 1, wherein the interconnect circuit comprises a first stage and a second stage for transferring the configuration data set from the configuration storage circuits to the configurable circuit, wherein the first stage receives the configuration data set from a set of configuration storage circuits and the second stage holds the received configuration data set in order to propagate the received configuration data set to the configurable circuits, wherein the set of clocked storage circuits is in the first stage of the interconnect circuit.

13. The IC of claim 1, wherein each configuration data set includes only one logical bit.

14. The IC of claim 13, wherein the interconnect circuit supplies each configuration data bit as a single physical bit to the configurable circuit.

15. The IC of claim 13, wherein the interconnect circuit supplies each configuration data bit as two complementary physical bits to the configurable circuit.

16. The IC of claim 1, wherein each configuration data set includes more than one logical bit.

17. The IC of claim 1, wherein the interconnect circuit switchably connects the configurable circuit to different sets of configuration storage circuits to receive different configuration data sets in order to allow the configurable circuit to reconfigure while the IC is operating.

18. The IC of claim 1, wherein each set of configuration storage circuits includes only one configuration storage circuit.

19. The IC of claim 1, wherein each set of configuration storage circuits includes more than one configuration storage circuits.

20. An integrated circuit (“

IC”

) comprising;

a configurable circuit for configurably performing one of a plurality of operations based on configuration data;

a plurality of configuration storage circuits for storing a plurality of configuration data sets for the configurable circuit; and

an interconnect circuit for switchably connecting the configurable circuit to different sets of the configuration storage circuits to receive different configuration data sets, said interconnect circuit comprising a set of pulsed storage circuits for temporarily storing the different configuration data sets, wherein the set of pulsed storage circuits stores the received configuration data set when receiving a clock pulse that has a duration of less than half of a clock cycle.

21. The IC of claim 20, wherein the set of pulsed storage circuits is further for providing the received configuration data set to the configurable circuit after temporarily storing the configuration data set.

22. The IC of claim 20, wherein the set of pulsed storage circuits is further (i) for receiving different configuration data sets from different sets of configuration storage circuits at different instances in time and (ii) for temporarily storing each received particular configuration data set before providing the received particular configuration data set to the configurable circuit.

23. An electronic device comprising:

an integrated circuit (“

IC”

) comprising;

a configurable circuit for configurably performing one of a plurality of operations based on configuration data;

a plurality of configuration storage circuits for storing a plurality of configuration data sets for the configurable circuit; and

an interconnect circuit for switchably connecting the configurable circuit to different sets of the configuration storage circuits to receive different configuration data sets, said interconnect circuit comprising (i) a set of clocked storage circuits and (ii) a set of unclocked storage circuits for temporarily storing the different configuration data sets; and

a memory device for providing the configuration data to the IC.