On-chip integrated voltage-controlled variable inductor, methods of making and tuning such variable inductors, and design structures integrating such variable inductors

• US 8,138,876 B2
• Filed: 01/29/2008
• Issued: 03/20/2012
• Est. Priority Date: 01/29/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ding, Hanyi, Mina, Essam F., Woods, Wayne H.
• Primary Examiner(s): Enad, Elvin G
• Assistant Examiner(s): Chan, Tsz
• Application Number:
  US12/021,339
• Publication Number:
  US 20090189725A1
• Time in Patent Office: 1,512 Days
• Field of Search: 257/531, 333/174, 336/137, 336/200, 336/223, 336/232, 296/021
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 21/005 Inductances without magnetic core
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor

Abstract

On-chip integrated variable inductors, methods of making and tuning an on-chip integrated variable inductor, and design structures embodying a circuit containing the on-chip integrated variable inductor. The inductor generally includes a signal line configured to carry an electrical signal, a ground line positioned in proximity to the signal line, and at least one control unit electrically coupled with the ground line. The at least one control unit is configured to open and close switch a current path connecting the ground line with a ground potential so as to change an inductance of the signal line.

Claims

1. A structure comprising:

a chip including an integrated circuit and an interconnect structure for said integrated circuit, said interconnect structure including a first metallization level, a second metallization level different from said first metallization level, a first conductive path coupled with a ground potential, and a second conductive path coupled with the ground potential;

a signal line of an inductor disposed in said first metallization level of said interconnect structure, said signal line electrically coupled with said integrated circuit for communication of an electrical signal;

a first ground line of said inductor disposed in said first metallization level of said interconnect structure or in said second metallization level of said interconnect structure, said first ground line positioned proximate to said signal line, said first ground line having a first end and a second end opposite to said first end, said first end of said first ground line coupled with said first conductive path, and said second end of said first ground line coupled with said second conductive path; and

at least one control unit included in said integrated circuit, said at least one control unit disposed in said first conductive path, said at least one control unit configured to selectively open and close said first conductive path,

wherein said signal line has a first inductance value when said first conductive path is open, and said signal line has a second inductance value when said first conductive path is closed such that said first end of said first ground line is coupled by the first conductive path with the ground potential and said second end of said first ground line is coupled by the second conductive path with the ground potential.

2. The structure of claim 1 wherein said first ground line is located between said signal line and said integrated circuit.

3. The structure of claim 1 wherein said signal line is a first planar spiral winding, and said first ground line is a second planar spiral winding that underlies said first planar spiral winding.

4. The structure of claim 1 wherein said signal line is a first planar conductive line, and said first ground line is a second planar conductive line disposed in a spaced relationship with said first planar conductive line.

5. The structure of claim 1 further comprising:

a dielectric material surrounding said signal line and said first ground line, a portion of said dielectric material disposed between said signal line and said first ground line to prevent electrical conduction between said signal line and said first ground line.

6. The structure of claim 1 further comprising:

a capacitance shield disposed between said first ground line and said signal line.

7. The structure of claim 1 further comprising:

a second ground line positioned proximate to said signal line, said second ground line configured to be selectively coupled in a second current path with the ground potential, said second current path electrically isolated from said first current path, and said signal line having a third inductance value when said second ground line is coupled with the ground potential.

8. The structure of claim 7 wherein said interconnect structure includes a third metallization level disposed between said first metallization level and said second metallization level, said first ground line is contained in said second metallization level, said second ground line is contained in third metallization level, and said first ground line, said second ground line, and said signal line have a stacked arrangement in which between said second ground line is disposed vertically between said first ground line and said signal line.

9. The structure of claim 7 wherein said first ground line, said second ground line, and said signal line are contained said first metallization level, and said signal line is disposed laterally between said first ground line and said second ground line.

10. The structure of claim 7 wherein said first ground line and said second ground line are contained in said second metallization level.

11. The structure of claim 7 further comprising:

a third ground line positioned proximate to said signal line, said third ground line configured to be selectively coupled in a third current path with the ground potential, said third current path electrically isolated from said first and second current paths, and said signal line having a fourth inductance value when said third ground line is coupled with the ground potential.

12. The structure of claim 11 wherein said first ground line, said second ground line, and said signal line are contained in said first metallization level, and said third ground line is disposed in said second metallization level.

13. The structure of claim 1 wherein the ground line is a first linear strip, and the signal line is a linear strip aligned substantially parallel to the first linear strip.

14. The structure of claim 13 wherein the ground line is thinner than the signal line.

15. The structure of claim 13 wherein the ground line and the signal line have approximately equal lengths.

16. The structure of claim 1 wherein the ground line and the signal line have equivalent geometrical shapes.

17. The structure of claim 1 wherein said first ground line of said inductor is disposed in said second metallization level of said interconnect structure, and said second metallization level is located between said first metallization level and said integrated circuit.

18. A method of making a structure, the method comprising:

fabricating an integrated circuit on a semiconductor substrate to form a chip;

after the integrated circuit is fabricated, fabricating an interconnect structure on the chip, the interconnect structure including a first metallization level with a signal line of an inductor that is electrically coupled with the integrated circuit, a first conductive path coupled with a ground potential, and a second conductive path coupled with the ground potential; and

fabricating a first ground line of the inductor in the first metallization level of the interconnect structure or in a second metallization level of the interconnect structure that is proximate to the signal line,

wherein the first ground line is fabricated with a first end and a second end opposite to said first end, the first end of the first ground line is coupled with the first conductive path, the second end of the first ground line coupled with the second conductive path, the integrated circuit includes at least one control unit configured for selectively opening and closing the first conductive path said at least one control unit configured to selectively open and close said first conductive path, said signal line has a first inductance value when said first conductive path is open, and said signal line has a second inductance value when said first conductive path is closed such that said first end of said first ground line is coupled by the first conductive path with the ground potential and said second end of said first ground line is coupled by the second conductive path with the ground potential.

19. The method of claim 18 wherein the first ground line and the signal line are fabricated in the first metallization level.

20. The method of claim 18 further comprising:

fabricating a second ground line sufficiently proximate to the signal line such that the signal line has a third inductance value when the second ground line is coupled in a second current path with the ground potential and the second inductance value when the second current path is open; and

fabricating at least one control unit in the integrated circuit that is configured for selectively opening and closing the second current path.

21. A design structure embodied in a machine readable medium for designing and manufacturing a circuit, the circuit comprising:

a chip including an integrated circuit and an interconnect structure for said integrated circuit, said interconnect structure including a first metallization level, a second metallization level different from said first metallization level, a first conductive path coupled with a ground potential, and a second conductive path coupled with the ground potential;

a signal line of an inductor disposed in said first metallization level of said interconnect structure, said signal line electrically coupled with said integrated circuit for communication of an electrical signal;

a first ground line of said inductor disposed in said first metallization level of said interconnect structure or in said second metallization level of said interconnect structure, said first ground line positioned proximate to said signal line, said first ground line having a first end and a second end opposite to said first end, said first end of said first ground line coupled with said first conductive path, and said second end of said first ground line coupled with said second conductive path; and

at least one control unit included in said integrated circuit, said at least one control unit disposed in said first conductive path, said at least one control unit configured to selectively open and close said first conductive path,

wherein said signal line has a first inductance value when said first conductive path is open, and said signal line has a second inductance value when said first conductive path is closed such that said first end of said first ground line is coupled by the first conductive path with the ground potential and said second end of said first ground line is coupled by the second conductive path with the ground potential.

22. The design structure of claim 21 wherein said signal line is a first planar spiral winding and said ground line is a second planar spiral winding that underlies said first planar spiral winding.

23. The design structure of claim 21 wherein said signal line is a first planar conductive line and said ground line is a second planar conductive line disposed in a spaced relationship with said first planar conductive line.

24. The design structure of claim 21 wherein said circuit further comprises:

a capacitance shield disposed between said ground line and said signal line.

25. The design structure of claim 21 wherein said at least one control unit is configured to operate upon receipt of a control voltage signal to selectively open and close said current path.

26. The design structure of claim 21 wherein said at least one control unit is selected from the group consisting of field effect transistors, positive-intrinsic-negative diodes, and combinations thereof.