Combined image sensor and display device

• US 8,139,055 B2
• Filed: 06/11/2007
• Issued: 03/20/2012
• Est. Priority Date: 06/12/2006
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Brown, Christopher James
• Primary Examiner(s): Wang, Quan-Zhen
• Assistant Examiner(s): Li, Lin
• Application Number:
  US12/303,794
• Publication Number:
  US 20100231562A1
• Time in Patent Office: 1,744 Days
• Field of Search: 250/208.1, 250/214.1, 250/205, 250/370.09, 341/158, 341/143, 345/214, 345/207, 345/76, 345/81, 345/89, 345/102, 345/212, 348/308, 348/362, 348/207.99, 348/226.1, 348/222.1, 348/294, 600/301, 330/4.9, 257/291, 257/204, 257/72, 257/294, 313/506, 326/81, 382/124, 435/5
• US Class Current: 345/207
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/042 by opto-electronic means
• CPC Class Codes: G09G 2360/142 the light being detected by light detection means within each pixel
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

A combined image sensor and display device comprises an array of device elements (18), each of which comprises a display pixel (M4, C2, CLC). The display pixels have data inputs connected to column data lines (SL, 6,6′). The array includes sensor elements (10), each comprising a transistor (M1), an integrating capacitor (C1) and a photodiode (D1) connected together to an integrating node (11). The transistor (M1) is connected between column data lines (6,6′). The capacitor (C1) is connected to a control input (RS) which receives a first voltage during a sensing phase for switching off the transistor (M1) and a second voltage during a reading phase for enabling the transistor (M1).

Claims

1. A combined image sensor and display device comprising a plurality of device elements arranged as an array of rows and columns, each of a first set of the device elements comprising a display pixel having a data input, the data inputs of each column being connected to a respective column data line, each of a second set of the device elements comprising an image sensor element comprising a photodetecting element, a semiconductor amplifying element, and an integrating capacitor having a first electrode, which is connected to a control electrode of the amplifying element and a first electrode of the photodetecting element, and a second electrode connected to a control input, which is arranged to receive, during a sensing phase, a first voltage for disabling the amplifying element and for permitting integration by the capacitor of a photocurrent from the photodetecting element and to receive, during a reading phase, a second voltage for enabling the amplifying element, each of the amplifying elements having a main conduction path connected to at least one of the column data lines, each of the amplifying elements having a control electrode threshold absolute voltage below which the amplifying element is disabled and the photocurrent being such that the absolute value of the voltage at the control electrode remains below the threshold absolute voltage during the sensing phase.

2. A device as claimed in claim 1, in which the polarity of the photocurrent is such as to reduce the absolute value of the voltage at the control electrode during the sensing phase.

3. A device as claimed in claim 1, in which the main conduction path of each of the amplifying elements is connected between a pair of the column data lines.

4. A device as claimed in claim 1, in which the first set comprises all of the device elements.

5. A device as claimed in claim 1, in which the second set comprises fewer than all of the device elements.

6. A device as claimed in claim 1, in which each of the senior elements is distributed across a respective group of the device elements.

7. A device as claimed in claim 1, in which the sensing and reading phases are repeated cyclically.

8. A device as claimed in claim 1, in which each of the photodetecting elements is a photodiode.

9. A device as claimed in claim 8, in which each of the photodiodes is a lateral photodiode.

10. A device as claimed in claim 8, in which each of the photodiodes is a thin film diode.

11. A device as claimed in claim 1, in which each of the amplifying elements comprises a voltage-follower arrangement.

12. A device as claimed in claim 1, in which each of the amplifying elements comprises a first transistor.

13. A device as claimed in claim 12, in which each of the first transistors is a thin film transistor.

14. A device as claimed in claim 12, in which each of the first transistors is a field effect transistor.

15. A device as claimed in claim 14, in which each of the first transistors is connected as a source-follower, the control electrode comprises the transistor gate and the main conduction path comprises the source-drain path.

16. A device as claimed in claim 1, in which each of the sensor elements comprises a semiconductor resetting element having a control electrode connected to a reset input and being arranged, during a resetting phase, to charge the capacitor to a predetermined voltage.

17. A device as claimed in claim 16, in which each of the resetting elements has a main conduction path connected between the first electrode of the capacitor and a predetermined voltage source.

18. A device as claimed in claim 16, in which each of the resetting elements comprises a second transistor.

19. A device as claimed in claim 18, in which each of the second transistors is a thin film transistor.

20. A device as claimed in claim 16, comprising row reset inputs, each of which is connected to the reset inputs of the sensor elements of a respective row.

21. A device as claimed in claim 1, comprising row control inputs, each of which is connected to the control inputs of the sensor elements of a respective row.

22. A device as claimed in claim 1, in which each of at least some of the column data lines is connected to a respective biasing element.

23. A device as claimed in claim 22, in which each biasing element comprises a third transistor.

24. A device as claimed in claim 23, in which each third transistor is a thin film transistor.

25. A device as claimed in claim 1, comprising an active matrix addressing arrangement.

26. A device as claimed in claim 25, in which active matrix addressing arrangement is arranged to address each row of the sensor elements during a line blanking period of a corresponding row of the display pixels.

27. A device as claimed in claim 1, in which the display pixels are liquid crystal pixels.