Methods and apparatus for dynamic packet mapping

• US 8,139,612 B2
• Filed: 04/04/2006
• Issued: 03/20/2012
• Est. Priority Date: 04/04/2006
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Bai, Jinxia, Ganapathy, Chinnappa K., Sun, Thomas
• Primary Examiner(s): Harper, Kevin C
• Assistant Examiner(s): DECKER, CASSANDRA L
• Application Number:
  US11/398,156
• Publication Number:
  US 20070230490A1
• Time in Patent Office: 2,177 Days
• Field of Search: 370/474
• US Class Current: 370/479
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04L 49/9078 using an external memory or storage device
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04W 28/14 using intermediate storage
• CPC Class Codes: H04W 8/26 Network addressing or numbering for mobility support

Abstract

Methods and apparatus for dynamic packet mapping. A method is provided for mapping metric data to produce a decodable packet associated with a channel. The method includes obtaining a channel identifier associated with metric data, determining an available buffer from a plurality of buffers based on the channel identifier, writing the metric data to the available buffer, detecting when a decodable packet is formed in a selected buffer of the plurality of buffers, and outputting the decodable packet from the selected buffer. An apparatus includes a plurality of buffers and mapping logic that is configured to obtain a channel identifier associated with metric data, determine an available buffer based on the channel identifier, write the metric data to the available buffer, detect when a decodable packet is formed in a selected buffer, and output the decodable packet from the selected buffer.

Claims

1. A method for mapping metric data to produce a decodable packet associated with a logical channel, the method comprising:

iteratively filling a plurality of buffers equal in number to a number of logical channels to be handled simultaneously by;

obtaining a data mode associated with the metric data, wherein the metric data results from processing a ready slot of data from a transmission frame and comprises log likelihood ratio (LLR) metrics, wherein an address counter is set at a beginning of each slot and used to generate a read address for the ready slot of data, the address counter being increased every predetermined number of clock cycles depending on the data mode;

selecting an available buffer from the plurality of buffers, wherein the plurality of buffers are of various sizes to accommodate various packet sizes, with a largest buffer size being at least equal to a largest packet size, and the selection of an available buffer of a given size is dependent on the available buffer being at least equal in size to a size of the decodable packet associated with a transmitting pattern; and

writing the metric data to the selected buffer; and

emptying the plurality of buffers by;

detecting when a decodable packet is formed in the selected buffer of the plurality of buffers, wherein the decodable packet is mapped from the metric data; and

outputting the decodable packet from the selected buffer to decoding logic.

2. The method of claim 1, further comprising determining that the available buffer is a partially filled buffer associated with a channel identifier.

3. The method of claim 1, further comprising determining that the available buffer is an empty buffer.

4. The method of claim 1, further comprising determining the available buffer from the plurality of buffers using a round-robin technique.

5. The method of claim 1, further comprising detecting when the decodable packet is formed in the selected buffer of the plurality of buffers using a round-robin technique.

6. An apparatus for mapping metric data to produce a decodable packet associated with a logical channel, the apparatus comprising:

a plurality of buffers equal in number to a number of logical channels to be handled simultaneously; and

mapping logic configured to iteratively fill the plurality of buffers by being configured to obtain a data mode associated with the metric data wherein the metric data results from processing a ready slot of data from a transmission frame and comprises log likelihood ratio (LLR) metrics, wherein an address counter is set at a beginning of each slot, and used to generate a read address for the ready slot of data, the address counter being increased every predetermined number of clock cycles depending on the data mode;

the mapping logic further configured to select an available buffer from the plurality of buffers, wherein the plurality of buffers are of various sizes to accommodate various packet sizes, with a largest buffer size being at least equal to a largest packet size, and the selection of an available buffer of a given size is dependent on the available buffer being at least equal in size to a size of the decodable packet associated with a transmitting pattern, and write the metric data to the selected buffer, and

the mapping logic further configured to empty the plurality of buffers by being configured to detect when a decodable packet is formed in the selected buffer of the plurality of buffers, and output the decodable packet from the selected buffer to decoding logic.

7. The apparatus of claim 6, wherein the mapping logic is configured to determine that the available buffer is a partially filled buffer associated with a channel identifier.

8. The apparatus of claim 6, wherein the mapping logic is configured determine that the available buffer is an empty buffer.

9. The apparatus of claim 6, wherein the mapping logic is configured determine the available buffer from the plurality of buffers using a round-robin technique.

10. The apparatus of claim 6, wherein the mapping logic is configured to detect when the decodable packet is formed in the selected buffer of the plurality of buffers using a round-robin technique.

11. An apparatus for mapping metric data to produce a decodable packet associated with a logical channel, the apparatus comprising:

means for iteratively filling a plurality of buffers equal in number to a number of logical channels to be handled simultaneously comprising;

means for obtaining a data mode associated with the metric data, wherein the metric data results from processing a ready slot of data from a transmission frame and comprises log likelihood ratio (LLR) metrics, wherein an address counter is set at a beginning of each slot, and used to generate a read address for the ready slot of data, the address counter being increased a first number of clock cycles depending on the data mode;

means for selecting an available buffer from the plurality of buffers, wherein the plurality of buffers are of various sizes to accommodate various packet sizes, with a largest buffer size being at least equal to a largest packet size, and the selection of an available buffer of a given size is dependent on the available buffer being at least equal in size to a size of the decodable packet associated with a transmitting pattern; and

means for writing the metric data to the selected buffer; and

means for emptying the plurality of buffers comprising;

means for detecting when a decodable packet is formed in the selected buffer of the plurality of buffers, wherein the decodable packet is mapped from the metric data; and

means for outputting the decodable packet from the selected buffer to decoding logic.

12. The apparatus of claim 11, further comprising means for determining that the available buffer is a partially filled buffer associated with a channel identifier.

13. The apparatus of claim 11, further comprising means for determining that the available buffer is an empty buffer.

14. The apparatus of claim 11, further comprising means for determining the available buffer from the plurality of buffers using a round-robin technique.

15. The apparatus of claim 11, wherein the means for detecting when the decodable packet is formed in the selected buffer of the plurality of buffers using a round-robin technique.

16. A non-transitory computer-readable medium having a computer program comprising instructions, which when executed by at least one processor, operate to map metric data to produce a decodable packet associated with a logical channel, the computer program comprising:

instructions for iteratively filling a plurality of buffers equal in number to a number of logical channels to be handled simultaneously comprising;

instructions for obtaining a data mode associated with the metric data, wherein the metric data results from processing a ready slot of data from a transmission frame and comprises log likelihood ratio (LLR) metrics, wherein an address counter is set at a beginning of each slot, and used to generate a read address for the ready slot of data, the address counter being increased every predetermined number of clock cycles depending on the data mode;

instructions for selecting an available buffer from the plurality of buffers, wherein the plurality of buffers are of various sizes to accommodate various packet sizes, with a largest buffer size being at least equal to a largest packet size, and the selection of an available buffer of a given size is dependent on the available buffer being at least equal in size to a size of the decodable packet associated with a transmitting pattern; and

instructions for writing the metric data to the selected buffer; and

instructions for emptying the plurality of buffers comprising;

instructions for detecting when a decodable packet is formed in the selected buffer of the plurality of buffers, wherein the decodable packet is mapped from the metric data; and

instructions for outputting the decodable packet from the selected buffer to decoding logic.

17. The computer-readable medium of claim 16, wherein the computer program further comprises instructions for determining that the available buffer is a partially filled buffer associated with a channel identifier.

18. The computer-readable medium of claim 16, wherein the computer program further comprises instructions for determining that the available buffer is an empty buffer.

19. The computer-readable medium of claim 16, wherein the computer program further comprises instructions for determining the available buffer from the plurality of buffers using a round-robin technique.

20. The computer-readable medium of claim 16, wherein the instructions for detecting when the decodable packet is formed in the selected buffer of the plurality of buffers use a round-robin technique.

21. An apparatus for mapping metric data to produce a decodable packet associated with a logical channel, the apparatus comprising:

a plurality of buffers equal in number to a number of logical channels to be handled simultaneously;

a memory; and

a processor coupled with the memory and the plurality of buffers, wherein the memory stores software codes comprising instructions implemented by the processor to iteratively fill the plurality of buffers using instructions to

a) obtain a data mode associated with the metric data, wherein the metric data results from processing a ready slot of data from a transmission frame and comprises log likelihood ratio (LLR) metrics, wherein an address counter is set at a beginning of each slot, and used to generate a read address for the ready slot of data, the address counter being increased every predetermined number of clock cycles depending on the data mode;

b) select an available buffer from the plurality of buffers, wherein the plurality of buffers are of various sizes to accommodate various packet sizes, with a largest buffer size being at least equal to a largest packet size, and the selection of an available buffer of a given size is dependent on the available buffer being at least equal in size to a size of the decodable packet associated with a transmitting pattern; and

c) write the metric data to the selected buffer; and

wherein the memory further stores software codes comprising instructions implemented by the processor to empty the plurality of buffers using instructions to

d) detect when a decodable packet is formed in the selected buffer of the plurality of buffers, wherein the decodable packet is mapped from the metric data; and

e) output the decodable packet from the selected buffer to decoding logic.

22. The apparatus of claim 21, wherein the software codes further comprise instructions implemented by the processor to determine that the available buffer is a partially filled buffer associated with a channel identifier.

23. The apparatus of claim 21, wherein the software codes further comprise instructions implemented by the processor to determine that the available buffer is an empty buffer.

24. The apparatus of claim 21, wherein the software codes further comprise instructions implemented by the processor to determine the available buffer from the plurality of buffers using a round-robin technique.

25. The apparatus of claim 21, wherein the instructions to detect when the decodable packet is formed in the selected buffer of the plurality of buffers use a round-robin technique.