High-speed receiver architecture

• US 8,139,630 B2
• Filed: 12/15/2008
• Issued: 03/20/2012
• Est. Priority Date: 10/03/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: ClariPhy Communications Incorporated (Inphi Corporation)
• Inventors: Agazzi, Oscar E., Crivelli, Diego E., Grace, Carl, Carrer, Hugo S., Hueda, Mario R., Luna, German C.
• Primary Examiner(s): Anh, Sam K
• Application Number:
  US12/335,493
• Publication Number:
  US 20090185613A1
• Time in Patent Office: 1,191 Days
• Field of Search: 375/259, 375/316, 375/324, 375/346, 375/233, 375/341, 375/229, 375/230, 375/231, 375/232, 375/234, 375/235, 375/236, 379/387.02, 379/340, 379/398, 324/607, 341/126, 341/127, 341/128, 341/155, 341/156, 341/159, 333/18, 333/28.R, 708/300, 708/322, 708/323
• US Class Current: 375/232
• CPC Class Codes: H03M 1/0626 by filtering
• CPC Class Codes: H03M 1/0692 using a diminished radix representation, e.g. radix 1.95
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/1042 the look-up table containing corrected values for replacing the original digital values H03M1/1052 takes precedence
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/181 in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
• CPC Class Codes: H03M 1/42 Sequential comparisons in series-connected stages with no change in value of analogue signal
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 25/0204 of multiple channels
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection

Abstract

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Claims

1. A multi-channel equalizer comprising:

a feedforward equalizer (FFE) coupled to receive an interleaved signal from a plurality of different channels, the feedforward equalizer capable of applying different equalization coefficients to data bits received from the different channels;

a Viterbi decoder coupled to an output of the feedforward equalizer, the Viterbi decoder determining detected symbols based on a channel model of at least one of the different channels; and

a channel estimator coupled to receive the output of the feedforward equalizer and the output of the Viterbi decoder and produce an error feedback signal to adaptively update the equalization coefficients of the feedforward equalizer based on the error feedback signal, the channel estimator modeling a response of the at least one channel based on a Volterra series model of the at least one channel and providing an input to the Viterbi decoder indicative of the channel model.

2. The multi-channel equalizer of claim 1 wherein the Volterra series model is a weighted sum of input bits, products of input bits, and a constant term.

3. The multi-channel equalizer of claim 2, wherein the Volterra series model is a weighted sum of a constant, N individual input bits, and all possible products containing two or more of those N input bits.

4. The multi-channel equalizer of claim 2, wherein the Volterra series model is a weighted sum of a constant, the input bits, and all pair-wise, triple-wise, and quadruple wise products of four input bits.

5. The multi-channel equalizer of claim 2, wherein the channel estimator forces the constant term to a predetermined value that compensates for baseline wander.

6. The multi-channel equalizer of claim 2, wherein the channel estimator forces the constant term to zero in the Volterra series model.

7. The multi-channel equalizer of claim 2, wherein the channel estimator forces a coefficient of a linear term corresponding to a most recently received bit to a predetermined value that fixes a scaling factor for the channel estimator.

8. The multi-channel equalizer of claim 2, wherein the channel estimator forces a coefficient of a linear term corresponding to a most recently received bit to 1 in the Volterra series model.

9. The multi-channel equalizer of claim 2, wherein the channel estimator forces a coefficient of an oldest bit to a predetermined value that trains an anticausal response of the channel estimator.

10. The multi-channel equalizer of claim 2, wherein the channel estimator forces a coefficient of an oldest bit to 1 in the Volterra series model.

11. A method for equalizing an input signal comprising:

receiving a digital interleaved input signal from a plurality of channels;

equalizing the digital input signal using a feedforward equalizer (FFE) by applying different equalization coefficients to input bit from at least two different channels;

decoding the equalized signal using a Viterbi decoder to determine an output signal comprising detected symbols in the equalized digital input signal based on a channel model of at least one of the plurality of channels; and

comparing the equalized signals to the output signal to produce an error signal;

adaptively updating the equalization coefficients of the feedforward equalizer based on the error signal;

modeling a response of the at least one channel based on a Volterra series model of the at least one channel to generate the channel model; and

providing a feedback input to the Viterbi decoder indicative of the channel model.

12. The method of claim 11, wherein the Volterra series model is a weighted sum of input bits, products of input bits, and a constant term.

13. The method of claim 12, wherein the Volterra series model is a weighted sum of a constant, N individual input bits, and all possible products containing two or more of those N input bits.

14. The method of claim 12, wherein the Volterra series model is a weighted sum of a constant, the input bits, and all pair-wise, triple-wise, and quadruple wise products of four input bits.

15. The method of claim 12, further comprising forcing the constant term to a predetermined value that compensates for baseline wander.

16. The method of claim 12, further comprising forcing the constant term to zero in the Volterra series model.

17. The method of claim 12, further comprising forcing a coefficient of a linear term corresponding to a most recently received bit to a predetermined value that fixes a scaling factor for the channel estimator.

18. The method of claim 12, further comprising forcing a coefficient of a linear term corresponding to a most recently received bit to 1 in the Volterra series model.

19. The method of claim 12, further comprising, forcing a coefficient of an oldest bit to a predetermined value that train an anticausal response of the channel estimator.

20. The method of claim 12, further comprising, forcing a coefficient of an oldest bit to 1 in the Volterra series model.