Device and methods for biphasic pulse signal coding

• US 8,139,654 B2
• Filed: 08/08/2006
• Issued: 03/20/2012
• Est. Priority Date: 08/08/2005
• Status: Active Grant

• Current Assignee: University of Florida Research Foundation, Incorporated (State University System of Florida)
• Original Assignee: University of Florida Research Foundation, Incorporated (State University System of Florida)
• Inventors: Chen, Du, Harris, John G., Principe, Jose C.
• Primary Examiner(s): Joseph, Jaison
• Application Number:
  US12/063,099
• Publication Number:
  US 20080192841A1
• Time in Patent Office: 2,051 Days
• Field of Search: 375/259, 375/242, 375/243, 375/254, 320/132, 340/511
• US Class Current: 375/259
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: H03K 7/06 Frequency or rate modulation, i.e. PFM or PRM
• CPC Class Codes: H03M 1/125 Asynchronous, i.e. free-running operation within each conversion cycle
• CPC Class Codes: H03M 3/00 Conversion of analogue values to or from differential modulation
• CPC Class Codes: H03M 5/02 Conversion to or from representation by pulses
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828

Abstract

A method for coding time signals based on generating an asynchronous biphasic pulse train is provided. The method includes generating response signals based upon one or more input signals. A pulse comprises a positive pulse if a voltage of the response signal is greater than a predetermined positive voltage threshold. A pulse comprises a negative pulse if the voltage of the response signal is less than a predetermined negative voltage threshold. The method further includes a method for the reconstruction of a uniformly sampled version of the original signal.

Claims

1. A method of coding time signals based on generating an asynchronous biphasic pulse train, the method comprising:

generating a plurality of response signals based upon at least one input signal; and

generating a series of pulses, wherein a pulse comprises a positive pulse if a voltage of the response signal is greater than a predetermined positive voltage threshold, and wherein a pulse comprises a negative pulse if the voltage of the response signal is less than a predetermined negative voltage threshold, and where generation of a subsequent pulse in the series of pulses is blocked for a predetermined time interval following generation of a previous pulse in the series of pulses, further comprising reconstructing the input signal received at time t based upon biphasic encoded data, the reconstruction being performed based upon an initial condition

2. The method of claim 1, wherein each input signal comprises an electrical current, and wherein generating a response signal based upon the input signal comprises integrating the electrical current.

3. The method of claim 1, wherein the first and second pulse are generated such that each has a pulse width defining a refractory period that is less than the interval between when the first pulse is generated and when the second pulse is generated.

4. The method of claim 1, wherein encoding comprises biphasic encoding based upon the predetermined positive and negative voltage thresholds and a predefined integrator constant.

5. A method of coding time signals based on generating an asynchronous biphasic pulse train, the method comprising:

generating a plurality of response signals based upon at least one input signal; and

generating a series of pulses, wherein a pulse comprises a positive pulse if a voltage of the response signal is greater than a predetermined positive voltage threshold, and wherein a pulse comprises a negative pulse if the voltage of the response signal is less than a predetermined negative voltage threshold, and where generation of a subsequent pulse in the series of pulses is blocked for a predetermined time interval following generation of a previous pulse in the series of pulses, further comprising compressing encoded time signals by generating pulses at a peak pulse rate whenever an input signal is above a minimum threshold and generating pulses at a pulse rate that is slower than the peak pulse rate otherwise.

6. The method of claim 5, wherein each input signal comprises an electrical current, and wherein generating a response signal based upon the input signal comprises integrating the electrical current.

7. The method of claim 5, wherein the first and second pulse are generated such that each has a pulse width defining a refractory period that is less than the interval between when the first pulse is generated and when the second pulse is generated.

8. The method of claim 5, wherein encoding comprises biphasic encoding based upon the predetermined positive and negative voltage thresholds and a predefined integrator constant.

9. A device for coding time signals based on an asynchronous biphasic pulse train, the device comprising:

an integrator for generating a response signal by integrating an electrical current input supplied to the device;

a first comparator for generating a positive pulse if a voltage of the response signal is greater than a predetermined positive voltage threshold;

a second comparator for generating a negative pulse if a voltage of the response signal is less than a predetermined negative voltage; and

a reset circuit configured to reset the integrator a predetermined time interval after generation of a pulse by the first comparator or by the second comparator, wherein the reset circuit comprises a delay connected to an output of the first comparator and to an output of the second comparator for resetting the integrator if one of an output of the first comparator and an output of the second comparator is non-zero.

10. The device of claim 9, wherein the integrator comprises a capacitor connected at a first end to a non-inverting input of the first comparator and to an inverting input of the second comparator and connected at a second end to ground.

11. The device of claim 9, wherein the reset circuit comprises a logic gate connected to an output of the first comparator and to an output of the second comparator, and a delay buffer connected to an output of the logic gate.

12. The device of claim 11, wherein the reset circuit further comprises a switch connected to the delay buffer for blocking generation of a subsequent pulse during the predetermined time interval following generation of a previous pulse.

13. A system, comprising:

at least one computing device; and

a time signal reconstruction application executable in the at least one computing device, the time signal reconstruction application comprising;

logic that obtains an asynchronous biphasic pulse train generated from a time signal received at time t; and

logic that reconstructs the time signal received at time t based upon biphasic encoded data of the pulse train, the reconstruction being performed based upon an initial condition

14. The system of claim 13, wherein the time signal is a bounded signal bandlimited to {−

ω

, ω

}.