Methods and systems for determining a defect criticality index for defects on wafers

• US 8,139,844 B2
• Filed: 04/14/2008
• Issued: 03/20/2012
• Est. Priority Date: 04/14/2008
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Chen, Chien-Huei (Adam), Xiong, Yan, Zhang, Jianxin, Chang, Ellis, Fang, Tsung-Pao
• Primary Examiner(s): Evans, F. L.
• Application Number:
  US12/102,343
• Publication Number:
  US 20090257645A1
• Time in Patent Office: 1,436 Days
• Field of Search: None
• US Class Current: 382/145
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection

Abstract

Various methods and systems for determining a defect criticality index (DCI) for defects on wafers are provided. One computer-implemented method includes determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system. The method also includes determining a DCI for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect.

Claims

1. A computer-implemented method for determining a defect criticality index for defects on wafers, comprising:

determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system; and

determining a defect criticality index for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect, wherein the critical area information comprises a local critical area map.

2. The method of claim 1, wherein determining the defect criticality index is performed during inspection of the wafer by the inspection system.

3. The method of claim 1, further comprising determining defect criticality indexes for multiple defects detected on the wafer and filtering the multiple defects having the defect criticality indexes below a predetermined threshold.

4. The method of claim 1, further comprising determining defect criticality indexes for multiple defects detected on the wafer and filtering the multiple defects having the defect criticality indexes below a predetermined threshold from results of inspection as the inspection of the wafer is being performed by the inspection system.

5. The method of claim 1, further comprising determining detect criticality indexes for multiple defects detected on the wafer, ranking the multiple defects based on the defect criticality indexes, and performing one or more functions on the multiple defects based on the ranking.

6. The method of claim 1, wherein the critical area information further comprises critical area information for multiple types of fault mechanisms.

7. The method of claim 1, wherein the location of the defect with respect to the critical area information comprises a location of the defect within a critical area map.

8. The method of claim 1, wherein the critical area information is extracted from design data for the wafer.

9. The method of claim 1, further comprising determining the location of the detect with respect to the critical area information by aligning an image of the defect to a critical area map to determine a location of the defect in the design.

10. The method of claim 1, further comprising determining a location of the defect in the design by aligning an image of the defect to a design clip.

11. The method of claim 1, further comprising creating a critical radius map prior to inspection of the wafer from design data for the wafer, wherein the critical radius map is a critical area map in which each value in the critical area map is a radius of the size of the defect that can cause a limit in the design.

12. The method of claim 11, further comprising during the inspection of the wafer, sending a portion of the critical radius map corresponding to an area of the wafer being inspected to one or more image processors of the inspection system.

13. The method of claim 11, wherein determining the critical area information comprises when the defect is detected, extracting a local area of the critical radius map and creating the local critical area map by thresholding the critical radius map with the reported size of the defect.

14. The method of claim 11, wherein the critical radius map does not comprise the design data.

15. The method of claim 1, wherein determining the critical area information comprises when a defect is detected, extracting a design clip having a window size centered at the reported location of the defect, wherein the window size is greater than the sum of the uncertainty of the reported location of the defect and the uncertainty of the reported size of the defect, and determining the critical area information from polygons in the design clip.

16. The method of claim 15, wherein determining the defect criticality index comprises applying a probability distribution function to the critical area information and summing the probability.

17. The method of claim 15, wherein determining the defect criticality index comprises applying a probability distribution function to the critical area information and summing the probability, and wherein the probability distribution function reflects the uncertainty of the reported location of the defect and the uncertainty of the reported size of the defect.

18. A non-transitory computer-readable medium, comprising program instructions executable on a computer system for performing a computer-implemented method for determining a defect criticality index for defects on wafers, wherein the computer-implemented method comprises:

determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system; and

determining a defect criticality index for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect, wherein the critical area information comprises a local critical area map.

19. A system configured to determine a defect criticality index for defects on wafers, comprising:

an inspection subsystem configured to detect a defect on a wafer and to report a location of the defect and a size of the defect; and

a computer subsystem configured to;

determine critical area information for a portion of a design for the wafer surrounding the defect based on the reported location and the reported size of the defect; and

determine a defect criticality index for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect, wherein the critical area information comprises a local critical area map.