On die thermal sensor

• US 8,140,293 B2
• Filed: 06/29/2007
• Issued: 03/20/2012
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jeong, Chun-Seok, Park, Kee-Teok
• Primary Examiner(s): Huynh, Phuong
• Application Number:
  US11/819,810
• Publication Number:
  US 20080082290A1
• Time in Patent Office: 1,726 Days
• Field of Search: 702/99, 702/117, 702/127, 702/130, 702/132, 702/134, 702/135, 327/83, 327/138, 327/262
• US Class Current: 702/130
• CPC Class Codes: G01K 7/425 Thermal management of integrated systems
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

An on die thermal sensor (ODTS) for use in a semiconductor device includes a temperature information output unit for measuring an internal temperature of the semiconductor device to generate a temperature information code having temperature information, and updating the temperature information code according to a refresh period.

Claims

1. An on die thermal sensor (ODTS) for use in a semiconductor device, comprising:

a temperature information output unit for measuring an internal temperature of the semiconductor device to generate a temperature information code having temperature information, and updating the temperature information code in response to an external update signal based on a refresh period, wherein the temperature information output unit includes;

an external update signal output unit for outputting the external update signal in response to a refresh command signal in a normal mode and outputting the external update signal in response to a self-refresh oscillation signal in a self-refresh mode, wherein the external update signal output unit includes a logic gate for performing an OR operation on the refresh command signal and the self-refresh oscillation signal and the external update signal is produced in response to an output of the logic gate.

2. The ODTS as recited in claim 1, wherein the temperature information output unit further includes:

a temperature information code generation unit for generating the temperature information code and a plurality of flag signals by measuring the internal temperature of the semiconductor device,

wherein the temperature information code generation unit updates the temperature information code in response to the external update signal.

3. The ODTS as recited in claim 2, wherein the temperature information code indicates the measured temperature as a binary code with a sign and each of the plurality of flag signals varies according to the measured temperature.

4. The ODTS as recited in claim 3, wherein a period of the refresh command signal varies according to the temperature information code.

5. The ODTS as recited in claim 3, wherein a period of the self-refresh oscillation signal varies according to the number of activated ones of the flag signals.

6. The ODTS as recited in claim 1, wherein the external update signal output unit further includes:

a divider for dividing an input period of the output of the logic gate;

a delay for delaying an output of the divider; and

an external update signal generation unit for generating the external update signal in response to an output of the delay.

7. The ODTS as recited in claim 6, wherein the logic gate includes an OR gate for performing the OR operation on the refresh command signal and the self-refresh oscillation signal.

8. The ODTS as recited in claim 3, wherein the temperature information code generation unit includes:

a temperature measuring unit for measuring the internal temperature of the semiconductor device to output a measuring temperature code having information relating to the measured temperature, and an internal update signal informing an update of the measuring temperature code;

a temperature information converting unit for performing a preset operation to convert the measuring temperature code into the temperature information code and the plurality of flag signals and output the temperature information code with an update signal in response to the internal update signal or the external update signal; and

an operation controlling unit for generating an operating control signal to control an operating mode of the temperature measuring unit and generating a test mode signal to control an operating mode of the temperature information converting unit.

9. The ODTS as recited in claim 8, wherein the temperature measuring unit includes:

a temperature sensing unit for generating a temperature voltage and first and second variation voltages, wherein the temperature voltage decreases as the internal temperature increases, and each of the first and second variation voltages has a constant voltage level regardless of a temperature variation; and

an analog-to-digital converting unit for converting the temperature voltage having an analog value and outputting the measuring temperature code having a digital value and the internal update signal in response to the first and second variation voltages.

10. The ODTS as recited in claim 9, wherein the temperature sensing unit includes:

a voltage amplifying unit for amplifying a first base-emitter voltage to output the temperature voltage, wherein a first base-emitter voltage is in proportion to a first emitter current of a first bipolar junction transistor (BJT) and decreases as the internal temperature increases;

a current generating unit for generating a first current which increases as the internal temperature increases and a second current which decreases as the internal temperature increases;

a reference voltage generating unit for generating a reference voltage which has a constant voltage level regardless of temperature variation and is in proportion to a third current generated by summing the first and second current with a preset ratio; and

a voltage level adjusting unit for determining voltage levels of the first and second variation voltages by adjusting a voltage level of the reference voltage in response to an adjusting code.

11. The ODTS as recited in claim 10, wherein the voltage amplifying unit includes:

a differential amplifier for receiving the first base-emitter voltage as a negative input and a first dividing voltage as a positive input to amplify and output the inputs;

a driver for driving the temperature voltage in response to an output of the differential amplifier; and

a divider for dividing a voltage level of the temperature voltage by a preset value to thereby determine a voltage level of the first dividing voltage.

12. The ODTS as recited in claim 11, wherein the driver includes a PMOS transistor for driving its drain with a power supply voltage coupled to its source to provide the temperature voltage at the drain in response to the output of the differential amplifier coupled to its gate.

13. The ODTS as recited in claim 11, wherein the divider includes first and second resistors having preset resistances between a temperature voltage output node and a ground voltage, wherein the first dividing voltage is outputted at a common node of the first and second resistors.

14. The ODTS as recited in claim 10, wherein the current generating unit includes:

a first current generating unit for generating the first current by providing a first resistor having a preset resistance with the first base-emitter voltage; and

a second current generating unit for forming a cascade connection with the first current generating unit and generating the second current by providing a second resistor having a preset resistance with a second base-emitter voltage in proportion to a second emitter current of a second BJT,

wherein the first emitter current is multiple times larger than the second emitter current in magnitude.

15. The ODTS as recited in claim 10, wherein the reference voltage generating unit generates the reference voltage by providing a resistor having a preset resistance with the third current generated by summing a current that is M times larger than the first current and a current that is N times larger than the second current and M and N are integers.

16. The ODTS as recited in claim 10, wherein the voltage level adjusting unit includes:

a first adjusting unit for outputting an adjusting reference voltage by adjusting the voltage level of the reference voltage; and

a second adjusting unit for outputting the first and second variation voltages by adjusting the voltage level of the adjusting reference voltage,

wherein each voltage level of the adjusting reference voltage and the first and second variation voltages is determined according to the adjusting code.

17. The ODTS as recited in claim 16, wherein the voltage level adjusting unit further includes an adjusting code register for storing the adjusting code to transmit them to the first and second adjusting units.

18. The ODTS as recited in claim 16, wherein the voltage levels of the first and second variation voltages have a constant difference.

19. The ODTS as recited in claim 16, wherein the first adjusting unit includes:

a differential amplifier for receiving the reference voltage as a negative input and a second dividing voltage as a positive input to amplify and output a difference in the inputs;

a driver for driving the adjusting reference voltage in response to an output of the differential amplifier; and

a divider for dividing the voltage level of the adjusting reference voltage by a preset value to thereby determine a voltage level of the second dividing voltage.

20. The ODTS as recited in claim 19, wherein the driver includes a PMOS transistor for driving a power supply voltage coupled to its source to its drain as the adjusting reference voltage in response to the output of the differential amplifier coupled to its gate.

21. The ODTS as recited in claim 19, wherein the divider includes a variable resistor having a variable resistance according to the adjusting code, and a first resistor having a preset resistance between an adjusting reference voltage output node and a ground voltage, wherein the second dividing voltage is outputted at a common node of the variable resistor and the first resistor.

22. The ODTS as recited in claim 21, wherein the variable resistor includes:

a plurality of resistors, each resistor being connected in series and having a preset resistance; and

a plurality of switches, each switch connected with a corresponding one of the resistors in parallel and being controlled according to the adjusting code.

23. The ODTS as recited in claim 16, wherein the second adjusting unit includes:

a differential amplifier for receiving the adjusting reference voltage as a negative input and a third dividing voltage as a positive input to amplify and output a difference in the inputs;

a driver for driving the first variation voltage in response to an output of the differential amplifier; and

a divider for dividing the voltage level of the first variation voltage by a preset value to thereby determine voltage levels of the second variation voltage and the third dividing voltage.

24. The ODTS as recited in claim 23, wherein the driver includes a PMOS transistor for driving its drain with a power supply voltage coupled to its source and provide the first variation voltage at the drain in response to the output of the differential amplifier coupled to its gate.

25. The ODTS as recited in claim 23, wherein the divider includes first and second variable resistors having variable resistances according to the adjusting code, and a first resistor having a preset resistance between a first variation voltage output node and a ground voltage, wherein the second variation voltage is outputted at a common node of the first and second variable resistors, and the third dividing voltage is outputted at a common node of the second variable resistor and the first resistor.

26. The ODTS as recited in claim 25, wherein each of the first and second variable resistors includes:

a plurality of resistors, each resistor being connected in series and having a preset resistance; and

a plurality of switches, each switch connected with a corresponding one of the resistors in parallel and being controlled according to the adjusting code.

27. The ODTS as recited in claim 10, wherein the adjusting code is a feedback signal of the measuring temperature code in a test mode, and is a fuse code in the normal mode and the self-refresh mode.

28. The ODTS as recited in claim 9, wherein the analog-to-digital converting unit includes:

a clock oscillation unit for oscillating a clock signal in response to the operating control signal outputted from the operation controlling unit;

a comparison unit for comparing the voltage level of the temperature voltage with that of a tracking voltage and decreasing or increasing the measuring temperature code according to the comparison result to output the decreased or increased measuring temperature code with the internal update signal under the control of the clock signal; and

a voltage level determination unit for determining the voltage level of the tracking voltage based on the measuring temperature code in the normal mode or a first test code in a test mode,

wherein the voltage level of the tracking voltage is lower than that of the first variation voltage and is higher than that of the second variation voltage.

29. The ODTS as recited in claim 28, wherein the comparison unit includes:

a comparator for comparing the voltage level of the temperature voltage with that of the tracking voltage in response to the clock signal so as to determine an increase signal and a decrease signal under the control of the compared result;

an up-down counter for decreasing or increasing the measuring temperature code according to the increase signal and the decrease signal under the control of a first delay clock generated by delaying the clock signal by a predetermined time; and

an internal update signal output unit for delaying the clock signal by a preset time to output the internal update signal.

30. The ODTS as recited in claim 29, wherein the comparison unit further includes a filtering unit for filtering the increase and the decrease signals in order to prevent the up/down counter from performing a wrong operation.

31. The ODTS as recited in claim 28, wherein the voltage level determination includes:

a digital-to-analog converter (DAC) for converting an adjusted information code having a digital value into the tracking voltage having an analog value in response to the first and second variation voltages;

a multiplexer for selecting the measuring temperature code in the normal mode and the first test code in the test mode in response to the test mode signal outputted from the operation controlling unit; and

a decoder for decoding outputs of the multiplexer to transmit the adjusted information code to the DAC.

32. The ODTS as recited in claim 31, wherein the DAC includes:

a first bias determination unit for determining a voltage level of a first bias voltage by comparing a first output voltage with the first variation voltage, wherein the voltage level of the first output voltage is controlled by the voltage level of the first bias voltage;

a second bias determination unit for determining a voltage level of a second bias voltage by comparing a second output voltage with the second variation voltage, wherein the voltage level of the second output voltage is controlled by the voltage level of the second bias voltage; and

a tracking voltage output unit, enabled under the control of the adjusted information code, for determining the voltage level of the tracking voltage based on the first and second bias voltages.

33. The ODTS as recited in claim 32, wherein the first bias determination unit includes:

a current mirror circuit for determining the voltage level of the first output voltage based on the first bias voltage; and

a comparator for outputting the first bias voltage by comparing the first output voltage with the first variation voltage.

34. The ODTS as recited in claim 32, wherein the second bias determination unit includes:

a current mirror circuit for determining the voltage level of the second output voltage based on the second bias voltage; and

a comparator for outputting the second bias voltage by comparing the second output voltage with the second variation voltage.

35. The ODTS as recited in claim 32, wherein the tracking voltage output unit includes a current mirror circuit which is enabled under the control of the adjusted information code and determines the voltage level of the tracking voltage based on the first and second bias voltages.

36. The ODTS as recited in claim 8, wherein the temperature information converting unit includes:

an operation code generating unit for performing a preset operation on the measuring temperature code and a fuse signal in the normal mode or a second test code in a test mode, and outputting an operation code;

a driving unit for driving the operation code and outputting the temperature information code and the update signal informing an update of the temperature information code in response to the internal update signal or the external update signal; and

a flag signal output unit for determining the plurality of flag signals in response to the operation code.

37. The ODTS as recited in claim 36, wherein the operation code generating unit includes:

a code converter for converting the measuring temperature code into a two'"'"'s complement form;

a multiplexer for selecting one of the fuse signal and the second test code in response to the test mode signal outputted from the operation controlling unit; and

an operation unit for receiving outputs of the code converter and the multiplexer and performing a preset operation to generate the operation code OP_SODE.

38. The ODTS as recited in claim 36, wherein the driving unit includes:

an OR gate for performing an OR operation to the internal update signal and the external update signal; and

a driver for driving the temperature information code and the update signal by receiving an output of the OR gate and the operation code.

39. The ODTS as recited in claim 36, wherein the flag signal output unit controls more flag signals to be a logic high level as the internal temperature of the semiconductor device increases.

40. The ODTS as recited in claim 8, wherein the operation controlling unit receives an enable signal, a test mode enable signal, and a self-refresh signal from external so as to generate the operating control signal and the test mode signal, wherein the enable signal controls an entry of the normal mode, the test mode enable signal controls an entry of a test mode, and the self-refresh signal controls an entry of the self-refresh mode.

41. A semiconductor device, comprising:

a temperature information output unit for measuring an internal temperature of the semiconductor device to generate a temperature information code and a plurality of flag signals, and updating the temperature information code in response to an external update signal, wherein the temperature information output unit includes an external update signal output unit for outputting the external update signal based on a refresh command signal in a normal mode and outputting the external update signal based on a self-refresh oscillation signal in a self-refresh mode and the external update signal output unit includes a logic gate for performing an OR operation on the refresh command signal and the self-refresh oscillation signal and the external update signal is produced in response to an output of the logic gate;

a code storage unit for storing the temperature information code when the temperature information code is updated;

a memory controller for changing a period of the refresh command signal by reading the temperature information code stored in the code storage unit; and

a self-refresh oscillation unit for changing a period of the self-refresh oscillation signal in response to the plurality of flag signals.

42. The semiconductor device as recited in claim 41, wherein the temperature information code indicates the measured temperature as a binary code, and the plurality of flag signals vary according to the measured temperature.

43. The semiconductor device as recited in claim 42, wherein the temperature information output unit further includes:

a temperature measuring unit for measuring the internal temperature of the semiconductor device to output a measuring temperature code having information relating to the measured temperature, and an internal update signal informing an update of the measuring temperature code;

a temperature information converting unit for performing a preset operation to convert the measuring temperature code into the temperature information code and the plurality of flag signals and outputting the temperature information code with an update signal in response to the internal update signal or the external update signal; and

an operation controlling unit for generating an operating control signal to control an operating mode of the temperature measuring unit and generating a test mode signal to control an operating mode of the temperature information converting unit.

44. The semiconductor device as recited in claim 43, wherein the temperature measuring unit includes:

a temperature sensing unit for generating a temperature voltage and first and second variation voltages, wherein the temperature voltage decreases as the internal temperature increases, and each of the first and second variation voltages has a constant voltage level regardless of a temperature variation; and

an analog-to-digital converting unit for converting the temperature voltage having an analog value and outputting the measuring temperature code having a digital value and the internal update signal in response to the first and second variation voltages.

45. The semiconductor device as recited in claim 41, wherein the external update signal output unit includes:

a divider for dividing an input period of the output of the logic gate; and

a delay for delaying an output of the divider to output the external update signal.

46. The semiconductor device as recited in claim 45, wherein the logic gate includes an OR gate for performing the OR operation on the refresh command signal and the self-refresh oscillation signal.

47. The semiconductor device as recited in claim 43, wherein the operation controlling unit receives an enable signal, a test mode enable signal, and a self-refresh signal from external so as to generate the operating control signal and the test mode signal, wherein the enable signal controls an entry of the normal mode, the test mode enable signal controls an entry of a test mode, and the self-refresh signal controls an entry of the self-refresh mode.

48. The semiconductor device as recited in claim 42, wherein the code storage unit includes a register for receiving the update signal as a first input and the temperature information code as a second input so as to store the temperature information code when the update signal is activated.

49. The semiconductor device as recited in claim 41, wherein the memory controller reads the temperature information code stored in the code storage unit and changes the period of the refresh command signal when the temperature information code varies.

50. The semiconductor device as recited in claim 41, wherein the self-refresh oscillation unit changes the period of the self-refresh oscillation signal according to the number of activated ones of the plurality of flag signals.

51. The semiconductor device as recited in claim 50, wherein the self-refresh oscillation unit increases the period of the self-refresh oscillation signal as the number of activated ones of the plurality of flag signals decreases.

52. The semiconductor device as recited in claim 50, wherein the self-refresh oscillation unit decreases the period of the self-refresh oscillation signal as the number of activated ones of the plurality of flag signals increases.