Method and apparatus for arbitration on a full-duplex bus using dual phases

• US 8,140,729 B2
• Filed: 01/19/2010
• Issued: 03/20/2012
• Est. Priority Date: 11/05/1999
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Johas Teener, Michael D.
• Primary Examiner(s): Myers, Paul R
• Application Number:
  US12/690,019
• Publication Number:
  US 20100241775A1
• Time in Patent Office: 791 Days
• Field of Search: 710/243
• US Class Current: 710/243
• CPC Class Codes: G06F 13/3625 using a time dependent access
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means.

Claims

1. A method for requesting bus arbitration in a network comprising a bus, a master node, and one or more non-master nodes, the bus comprising a plurality of alternating phases having at least an even phase and an odd phase, the method comprising:

identifying if a first bus phase is even or odd;

determining whether bus arbitration is fair during the first bus phase; and

if bus arbitration during the first bus phase is not fair, queuing a request for bus arbitration, the request having an indicia identifying one of a plurality of exclusive second phases comprising a next odd phase and a next even phase;

wherein;

if the first bus phase is even, queuing the request for bus arbitration during the next odd phase; and

if the first bus phase is odd, queuing the request for bus arbitration during the next even phase.

2. The method of claim 1, wherein determining if bus arbitration is fair is based at least in part on all nodes wishing to gain control of the bus having at least one opportunity to arbitrate for the bus within the first bus phase.

3. The method of claim 1, wherein if bus arbitration during the first bus phase is not fair, issuing a notification indicating no arbitration for the first bus phase.

4. The method of claim 1, wherein the bus comprises one or more isochronous phases.

5. The method of claim 4, wherein the even and odd phases are asynchronous.

6. The method of claim 4, wherein the even phase is an even isochronous phase and the odd phase is an odd isochronous phase.

7. The method of claim 4, wherein each non-master node continuously broadcasts an intention, the intention being:

an intention to arbitrate, and an intention not to arbitrate.

8. A method for granting bus arbitration in a network comprising a bus, a master node, and one or more non-master nodes, the method comprising:

providing a plurality of exclusive bus phases comprising an even phase and an odd phase, each of the bus phases having a corresponding reset; and

for each phase;

issuing the corresponding reset;

receiving a plurality of requests for arbitration, the plurality of requests comprising;

(i) at least one request for bus arbitration requested during a current phase, (ii) at least one request for bus arbitration queued for a next even phase and (iii) at least one request for bus arbitration queued for a next odd phase;

granting bus arbitration for each of the received requests;

determining that advance to a next phase is fair; and

advancing to the next phase.

9. The method of claim 8, wherein advancing to the next phase comprises advancing to the odd phase when in the even phase, and advancing to the even phase when in the odd phase.

10. The method of claim 9, wherein the corresponding resets comprise an even reset and an odd reset.

11. The method of claim 8, wherein determining when advance to the next phase is fair is based at least in part on each of the received requests being granted within a fairness interval.

12. The method of claim 8 additionally comprising receiving a plurality of notifications indicating no arbitration requested during the current phase.

13. The method of claim 8, wherein one or more requests for bus arbitration during the next odd phase is/are received during even phases;

and

one or more requests for bus arbitration during the next even phase is/are received during odd phases.

14. A master node apparatus for granting bus arbitration, comprising:

at least one network interface, the at least one network interface having a plurality of exclusive bus phases comprising an even phase and an odd phase, each of the bus phases having a corresponding reset;

wherein for each phase, the at least one network interface is configured to issue the corresponding reset and receive a plurality of requests for arbitration; and

wherein the plurality of requests comprises;

(i) requests for bus arbitration requested during a current phase, (ii) requests for bus arbitration during a next even phase and (iii) requests for bus arbitration during a next odd phase;

a processor; and

a computer readable apparatus comprising a storage medium storing at least one computer program, the at least one program comprising a plurality of instructions configured to, when executed by a processor;

queue the plurality of received requests for bus arbitration;

grant bus arbitration for one or more received requests; and

advance to the next phase.

15. The master node apparatus of claim 14, wherein the bus comprises one or more isochronous phases.

16. The master node apparatus of claim 15, wherein the even and odd phases are asynchronous.

17. The master node apparatus of claim 14, wherein the even and odd phases are isochronous.

18. A non-master node apparatus for requesting bus arbitration, comprising:

at least one network interface, the at least one network interface having a plurality of exclusive bus phases comprising an even phase and an odd phase;

wherein the at least one network interface is configured to transmit an intention message, the intention message being selected from;

an intention to arbitrate message, and an intention not to arbitrate message;

wherein the intention to arbitrate message comprises an indication of (i) a current phase, (ii) a next even phase and (iii) a next odd phase;

a processor; and

a computer readable apparatus comprising a storage medium storing at least one computer program, the at least one program comprising a plurality of instructions which, when executed by the processor, for each phase;

determines whether or not the non-master node needs to arbitrate for the bus;

if the non-master node needs to arbitrate, then determines the indication; and

generates the intention message.

19. The non-master node apparatus of claim 18, additionally comprising a second network interface, the second network interface configured to receive one or more peer intention messages from other non-master nodes.

20. The non-master node apparatus of claim 19, wherein the determination of whether or not the non-master node needs to arbitrate for the bus comprises a first priority, and where the one or more peer intention messages comprise at least a second priority;

and

wherein the at least one computer program additionally comprises instruction which when executed by the processor;

determines the highest priority device; and

generates the intention message based at least in part on the highest priority device.