Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store files having logical block addresses stored in a write frequency file buffer table

• US 8,140,739 B2
• Filed: 08/08/2008
• Issued: 03/20/2012
• Est. Priority Date: 08/08/2008
• Status: Expired due to Fees

• Current Assignee: SPEX Technologies, Inc.
• Original Assignee: Imation Corporation (Glassbridge Enterprises, Inc.)
• Inventors: Langlois, Denis J., Olson, Alan R.
• Primary Examiner(s): Kim, Hong
• Application Number:
  US12/228,033
• Publication Number:
  US 20100037001A1
• Time in Patent Office: 1,320 Days
• Field of Search: 711/103, 711/3, 711/5, 711/117, 711/118, 711/161, 711/202, 365/158
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.

Claims

1. A storage device comprising:

flash memory;

a host interface for communicating with a host device;

a processor that receives commands from the host device via the host interface and coordinates at least one of addressing, programming, erasing and reading of data to or from the flash memory;

a buffer electrically connected between the host interface and the flash memory; and

a high write volume magnetoresistive random access memory (MRAM) electrically connected between the host interface and a flash controller,

wherein the processor compares a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table, causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table and a size of the data file is less than or equal to an available space in the high write volume MRAM, and causes the data file to be written to the flash memory when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table and the size of the data file is greater than the available space in the high write volume MRAM memory.

2. The storage device of claim 1, wherein the storage device is a solid state drive (SSD).

3. The storage device of claim 1, wherein the processor causes the data file to be written to the flash memory when the logical block address of the data file does not match any of the plurality of logical block addresses stored in the write frequency file buffer table.

4. The storage device of claim 1, further comprising a MRAM device memory that stores the write frequency file buffer table.

5. The storage device of claim 4, wherein the MRAM device memory stores a MRAM translation layer and a flash translation layer, wherein the MRAM translation layer comprises the write frequency file buffer table and a MRAM address map, and wherein the flash translation layer comprises at least one of erase count tables and flash translation layer tables.

6. The storage device of claim 5, wherein the processor causes the MRAM translation layer and the flash translation layer to be stored in the MRAM device memory without causing writing of the control information to the flash memory.

7. A method comprising:

comparing a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer; and

writing the data file to a high write volume magnetoresistive random access memory (MRAM) when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer and a size of the data file is less than or equal to an available space in the high write volume MRAM; and

writing the data file to a flash memory when the logical block address of the file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer and the size of the data file is greater than the available space in the high write volume MRAM.

8. The method of claim 7, further comprising:

updating an MRAM translation layer address table with the physical address at which the data file is written.