Information handling system with immediate scheduling of load operations and fine-grained access to cache memory

• US 8,140,756 B2
• Filed: 04/15/2009
• Issued: 03/20/2012
• Est. Priority Date: 04/15/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Guthrie, Guy Lynn, Powell, Stephen, Starke, William John, Gai, Sanjeev
• Primary Examiner(s): Le, Vu
• Application Number:
  US12/424,332
• Publication Number:
  US 20100268883A1
• Time in Patent Office: 1,070 Days
• Field of Search: 711/118, 711/119, 711/167, 711/158
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831

Abstract

An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption. The control logic determines the size requirement of each load operation or store operation. When the cache memory system performs a store operation or load operation, the memory system accesses the portion of a cache line it needs to perform the operation instead of accessing an entire cache line.

Claims

1. A method comprising:

sending, by a processor element, a plurality of requests for memory operations to a cache memory, the memory operations including load operations and store operations, the store operations exhibiting respective size requirements;

determining, by control logic, the respective size requirements of the store operations in the plurality of requests;

performing a first cache memory access, by the cache memory, in response to a load operation request; and

performing a second cache memory access, by the cache memory, in response to a store operation request, the second cache memory access being limited in size to the size requirement for the store operation determined by the control logic.

2. The method of claim 1, further comprising arbitrating, by an arbitration mechanism, to determine an order in which the cache memory performs load and store operations, wherein load operations receive priority over store operations.

3. The method of claim 1, further comprising performing a third cache memory access, by the cache memory, in response to a load operation request, the cache memory performing the third cache memory access immediately after the second cache memory access.

4. The method of claim 1, wherein the size requirement of a store operation is a minimum number of cycles that the store operation takes to complete in the cache memory.

5. The method of claim 1, wherein the size requirement of a store operation is a minimum number of bytes that the store operation requires to access in cache memory to complete the store operation.

6. The method of claim 1, wherein the cache memory is an L2 cache memory.

7. The method of claim 1, wherein the processor element is a processor core that includes an L1 cache memory.

8. A cache memory system comprising:

a processor element; and

a cache memory, coupled to the processor element, wherein the processor element sends plurality of requests for memory operations to the cache memory, the memory operations including load operations and store operations, the store operations exhibiting respective size requirements;

the cache memory including control logic that determines the respective size requirements of the store operations in the plurality of requests, wherein the cache memory performs a first cache memory access in response to a load operation request, wherein the cache memory performs a second cache memory access in response to a store operation request, the second cache memory access being limited in size to the size requirement for the store operation determined by the control logic.

9. The cache memory system of claim 8, wherein the cache memory includes an arbitration mechanism that arbitrates to determine an order in which the cache memory performs load and store operations, wherein load operations receive priority over store operations.

10. The cache memory system of claim 8, wherein the cache memory performs a third cache memory access in response to a load operation request, the cache memory performing the third cache memory access immediately after the second cache memory access.

11. The cache memory system of claim 8, wherein the size requirement of a store operation is a minimum number of cycles that the store operation takes to complete in the cache memory.

12. The cache memory system of claim 8, wherein the size requirement of a store operation is a minimum number of bytes that the store operation requires to access in cache memory to complete the store operation.

13. The cache memory system of claim 8, wherein the cache memory is an L2 cache memory.

14. The cache memory system of claim 8, wherein the processor element is a processor core that includes an L1 cache memory.

15. A information handling system (IHS) comprising:

a processor element;

a cache memory, coupled to the processor element, wherein the processor element sends plurality of requests for memory operations to the cache memory, the memory operations including load operations and store operations, the store operations exhibiting respective size requirements;

the cache memory including control logic that determines the respective size requirements of the store operations in the plurality of requests, wherein the cache memory performs a first cache memory access in response to a load operation request, wherein the cache memory performs a second cache memory access in response to a store operation request, the second cache memory access being limited in size to the size requirement for the store operation determined by the control logic; and

a system memory coupled to the cache memory.

16. The information handling system (IHS) of claim 15, wherein the cache memory includes an arbitration mechanism that arbitrates to determine an order in which the cache memory performs load and store operations, wherein load operations receive priority over store operations.

17. The information handling system (IHS) of claim 15, wherein the cache memory performs a third cache memory access in response to a load operation request, the cache memory performing the third cache memory access immediately after the second cache memory access.

18. The information handling system (IHS) of claim 15, wherein the size requirement of a store operation is a minimum number of cycles that the store operation takes to complete in the cache memory.

19. The information handling system (IHS) of claim 15, wherein the size requirement of a store operation is a minimum number of bytes that the store operation requires to access in cache memory to complete the store operation.

20. The information handling system (IHS) of claim 15, wherein the cache memory is an L2 cache memory.

21. The information handling system (IHS) of claim 15, wherein the processor element is a processor core that includes an L1 cache memory.