I-cache line use history based done bit based on successful prefetchable counter

• US 8,140,760 B2
• Filed: 05/28/2009
• Issued: 03/20/2012
• Est. Priority Date: 05/28/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David A.
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Norman, James G
• Application Number:
  US12/473,337
• Publication Number:
  US 20100306472A1
• Time in Patent Office: 1,027 Days
• Field of Search: None
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/127 using additional replacement algorithms

Abstract

A method of providing history based done logic for a I-cache includes receiving an I-cache line in an L2 cache; determining if the I-cache line is unprefetchable; aging the I-cache line without a delay if the I-cache line is prefetchable; and aging the I-cache line with a delay is the I-cache line is unprefetchable.

Claims

1. A method of providing history based done logic for an I-cache, the method comprising:

receiving an I-cache line in an L2 cache;

determining if the I-cache line is unprefetchable;

aging the I-cache line without a delay if the I-cache line is prefetchable; and

aging the I-cache line with a delay if the I-cache line is unprefetchable;

wherein the I-cache line includes a demand stall flag, an aging flag, a history count and a reference count.

2. The method of claim 1, wherein the determining further comprises updating the reference count in an L1 I-cache and the L2 I-cache each time the I-cache line is accessed.

3. The method of claim 1, further comprising aging the I-cache line at a rate indicated by the aging flag if a demand stall flag indicates that I-cache line is unprefetchable.

4. An integrated circuit device comprising:

a processor core;

a level one (L1) cache;

a level two (L2) cache;

an aging count in the L1cache for indicating a number of least recently used demotions to be skipped between actual demotions to an I-cache line in the L1 cache, wherein the I-cache line includes a demand stall flag and an aging flag;

a counter that counts each time the I-cache line is referenced in the L1 cache; and

a comparator for comparing a history count to a reference count to determine when the reference count is equal to the history count for an I-cache line.

5. The integrated circuit device of claim 4, wherein the counter updates a reference counter in the L2 cache each time the I-cache line is referenced in the L1cache.

6. The integrated circuit device of claim 4, wherein the I-cache line is aged at a rate indicated by the aging flag if a demand stall flag indicates that I-cache line is unprefetchable.

7. A processor device, comprising:

a level one (L1) cache;

a level two (L2) cache;

circuitry configured to receive an I-cache line in the L2 cache, determine if the I-cache line is unprefetchable, age the I-cache line without a delay if the I-cache line is prefetchable; and

age the I-cache line with a delay if the I-cache line is unprefetchable;

wherein the I-cache line includes a demand stall flag, an aging flag, a history count and a reference count.

8. The processor device of claim 7, wherein determining further comprises updating the reference count in the L1 I-cache and the L2 I-cache each time the I-cache line is accessed.

9. The processor device of claim 7, further comprising aging the I-cache line at a rate indicated by the aging flag if a demand stall flag indicates that I-cache line is unprefetchable.