Memory component having write operation with multiple time periods
First Claim
1. A memory system, comprising:
- a communication channel coupled to a controller and coupled to a memory device;
the controller to generate control information and data information, including at least two write commands to the memory device followed by another command and then followed by a read command to the memory device, wherein respective data information corresponds to respective control information, the other command is between the at least two write commands and the read command; and
the memory device to receive the control information and the data information in a same order as generated by the controller and to process the read command prior to completing the processing of one of the at least two write commands;
wherein the memory device comprises;
a memory core having dynamic random access memory cells;
a first interface to receive the two write commands, each specifying a write operation;
a first circuit to store a respective write command for a first time period;
a second interface to receive data associated with the respective write operation, wherein receipt of the data occurs based on a second time period, wherein the second time period follows the first time period, such that receipt of the respective write command and the data are separated by a delay time that includes both the first time period and the second time period.
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Abstract
A memory component includes a memory core, a control transport block to receive a write command from external control lines, and a write control buffer to store the write command for a first time period after the write command is received at the transport block. A data buffer receives data from external data lines, the data to be stored in the memory core in response to the write command, wherein receipt of the data occurs based on a second time period that follows the first time period, such that receipt of the write command and the data are separated by a delay time that includes both the first time period and the second time period. A write mask buffer receives write masking information from an external write mask line. Receipt of the write command and the write masking information are separated by the delay time.
189 Citations
23 Claims
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1. A memory system, comprising:
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a communication channel coupled to a controller and coupled to a memory device; the controller to generate control information and data information, including at least two write commands to the memory device followed by another command and then followed by a read command to the memory device, wherein respective data information corresponds to respective control information, the other command is between the at least two write commands and the read command; and the memory device to receive the control information and the data information in a same order as generated by the controller and to process the read command prior to completing the processing of one of the at least two write commands; wherein the memory device comprises; a memory core having dynamic random access memory cells; a first interface to receive the two write commands, each specifying a write operation; a first circuit to store a respective write command for a first time period; a second interface to receive data associated with the respective write operation, wherein receipt of the data occurs based on a second time period, wherein the second time period follows the first time period, such that receipt of the respective write command and the data are separated by a delay time that includes both the first time period and the second time period.
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2. A memory component, comprising:
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a memory core having dynamic random access memory cells; a first interface to receive a write command that specifies a write operation; a first circuit to store the write command for a first time period; a second interface to receive data associated with the write operation, wherein receipt of the data occurs based on a second time period, wherein the second time period follows the first time period, such that receipt of the write command and the data are separated by a delay time that includes both the first time period and the second time period. - View Dependent Claims (3, 4, 5)
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6. A memory component comprising:
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a memory core including an array of memory cells; a control transport block to receive a write command from external control lines, wherein the write command specifies a write operation; a write control buffer coupled to the control transport block, the write control buffer to store the write command for a first time period after the write command is received at the transport block; a data buffer to receive data from external data lines, the data to be stored in the memory core in response to the write command, wherein receipt of the data occurs based on a second time period, wherein the second time period follows the first time period, such that receipt of the write command and the data are separated by a delay time that includes both the first time period and the second time period; and a write mask buffer to receive write masking information from an external write mask line, wherein the write masking information specifies whether to mask portions of the data to be written to the memory core during the write operation, wherein receipt of the write command and the write masking information are separated by the delay time. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A method of operation of a memory component that includes a memory core having dynamic random access memory cells, the method comprising:
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at a first interface of the memory component, receiving a write command, wherein the write command specifies a write operation; after receiving the write command, storing the write command for a first time period; and at a second interface of the memory component, receiving data associated with the write operation, wherein receipt of the data occurs after a second time period transpires, the second time period following the first time period, such that receiving the write command and receiving the data are separated by a delay time that includes both the first time period and the second time period. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method of operation of a memory component that includes a memory core having dynamic random access memory cells, the method comprising:
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at a first interface of the memory component, receiving a write command, wherein the write command specifies a write operation; after receiving the write command, storing the write command for a first time period, at a second interface of the memory component, receiving data associated with the write operation, wherein receipt of the data occurs after a second time period transpires, the second time period following the first time period, such that receiving the write command and receiving the data are separated by a delay time that includes both the first time period and the second time period; and receiving mask information that indicates whether to mask portions of the data to be written to the memory core during the write operation, wherein receiving the write command and receiving the mask information are separated by the delay time that includes both the first time period and the second time period. - View Dependent Claims (20, 21, 22, 23)
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Specification