Restoring processor context in response to processor power-up

• US 8,140,872 B1
• Filed: 06/10/2008
• Issued: 03/20/2012
• Est. Priority Date: 06/16/2000
• Status: Expired due to Term

• Current Assignee: Complex Memory LLC (IPValuation Partners, LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Fleischmann, Marc, Anvin, H. Peter
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US12/136,679
• Time in Patent Office: 1,379 Days
• Field of Search: 713/300, 713/320
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3246 by software initiated power-off
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.

Claims

1. A method comprising:

executing, with a processor, a first instruction in an instruction set;

subsequent to said executing and before executing a next instruction in said instruction set following said first instruction, and in response to detecting a command to remove a clock input from said processor, saving context information from said processor'"'"'s internal memory to a second memory and then removing power from said processor;

in response to returning power to said processor, restoring said saved context information from said second memory to said internal memory before executing said next instruction; and

subsequent to said restoring, executing said next instruction.

2. The method of claim 1 wherein said second memory and said processor are in different power domains.

3. The method of claim 1 wherein said internal memory and said processor are in different power domains.

4. The method of claim 1 further comprising:

setting a flag in response to said removing power; and

checking said flag in response to said returning power.

5. The method of claim 1 further comprising:

measuring an amount of time after said first instruction is executed before said next instruction is executed; and

subsequent to said executing and before executing said next instruction, and if said amount of time equals or exceeds a threshold, saving said context information from said processor'"'"'s internal memory to said second memory and then removing said power from said processor.

6. The method of claim 1 further comprising, after said removing power, monitoring a user input device for a sign of activity, wherein said returning power is performed in response to detecting said sign.

7. A computer-readable storage device having stored thereon, computer-executable instructions that, responsive to execution by a computing device, cause the computing device to perform operations comprising:

subsequent to a processor executing a first instruction in an instruction set and before said processor executes a next instruction in said instruction set following said first instruction, and in response to detecting a command to remove a clock input from said processor, saving context information from said processor'"'"'s internal memory to a second memory and then removing power from said processor;

in response to a triggering event, returning power to said processor and restoring said saved context information from said second memory to said internal memory before said next instruction is executed; and

subsequent to said restoring, executing said next instruction.

8. The computer-readable storage device of claim 7 wherein said operations further comprise powering said second memory and said processor independently from one another.

9. The computer-readable storage device of claim 7 wherein said operations further comprise powering said internal memory and said processor independently from one another.

10. The computer-readable storage device of claim 7 wherein said operations further comprise:

setting a flag in response to said removing power; and

checking said flag in response to said returning power.

11. The computer-readable storage device of claim 7 wherein said operations further comprise:

measuring an amount of time after execution of said first instruction and before execution of said next instruction; and

subsequent to said executing and before executing said next instruction, and if said amount of time equals or exceeds a threshold, saving said context information from said processor'"'"'s internal memory to said second memory and then removing said power from said processor.

12. The computer-readable storage device of claim 7 wherein said operations further comprise, after said removing power, monitoring a user input device for a signal, wherein said returning power is performed in response to detecting said signal.

13. A computer system comprising:

a processor operable for executing a first instruction and a second instruction in an instruction set, wherein said first instruction and said second instruction are consecutive; and

a memory coupled to said processor, wherein said memory is configured to remain powered if said processor is powered down;

wherein after executing said first instruction and before executing said second instruction, and in response to detecting a command to remove a clock input from said processor, said processor is operable for saving context information from said processor'"'"'s internal memory to said memory;

wherein if said processor is powered down after said context information is saved to said memory, then said saved context information is restored from said memory to said internal memory in response to powering up said processor and before said second instruction is executed, wherein said processor is then operable for executing said second instruction.

14. The computer system of claim 13 wherein said internal memory is configured to remain powered if said processor is powered down.

15. The computer system of claim 13 wherein a flag is set in response to powering down said processor.

16. The computer system of claim 13 wherein said processor is further configured to be powered down in response to determining that an amount of time between execution of said first instruction and execution of said second instruction equals or exceeds a threshold.

17. The computer system of claim 13 further comprising a user input device coupled to said processor, wherein said processor is configured to be powered up in response to detecting a signal from said user input device.

18. An apparatus comprising:

means for executing a first instruction in an instruction set;

means for detecting a command to remove a clock input from said means for executing;

means for saving context information associated with said means for executing, said context information saved after said first instruction is executed and before a next instruction in said instruction set is executed, in response to detecting said command; and

means for restoring said context information to said means for executing if power is removed from said means for executing after said first instruction is executed and if power is then returned to said means for executing before said next instruction is executed, wherein said next instruction is executable after said context information is restored.