Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

• US 8,140,925 B2
• Filed: 06/26/2007
• Issued: 03/20/2012
• Est. Priority Date: 06/26/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bellofatto, Ralph E., Ellavsky, Matthew R., Gara, Alan G., Giampapa, Mark E., Gooding, Thomas M., Haring, Rudolf A., Hehenberger, Lance G., Ohmacht, Martin
• Primary Examiner(s): Gaffin, Jeffrey A
• Assistant Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US11/768,791
• Publication Number:
  US 20090006894A1
• Time in Patent Office: 1,729 Days
• Field of Search: 714/731
• US Class Current: 714/731
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Claims

1. An apparatus for evaluating a logic state of an integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, each said IC supporting multiple synchronous frequency clock domains, said apparatus comprising:

a first circuit means for generating a synchronized set of enable signals in correspondence with multiple IC sub-units for starting operation of multiple IC sub-units according to a determined timing configuration; and

a second circuit means responsive to one signal of said synchronized set of enable signals to start counting a number of clock cycles of a fastest processor clock operating on said chip and, upon attaining a pre-specified clock cycle number, generating a stop signal for each unique frequency clock domain associated with a different clock frequency of said multiple synchronous frequency clock domains, said stop signals output in parallel to synchronously stop a respective functional clock operating at said different clock frequency for each respective synchronous frequency clock domain,

wherein all on-chip functional clocks are synchronously stopped on all frequency clock domains in a deterministic fashion to place said IC in a state for scanning out IC logic state data values for debugging a logic design flaw from said IC.

2. The apparatus as claimed in claim 1, wherein said first circuit means provides configuration signals for configuring operation of said IC sub-units at a determined point in time with respect to all clock edges of functional clocks at said different clock frequencies implemented in respective frequency clock domains supported by said IC.

3. The apparatus as claimed in claim 1, wherein said determined timing configuration for starting operation of one or more IC sub-units is in synchrony with all on-chip functional clocks.

4. The apparatus as claimed in claim 1, wherein said synchronized set of enable signals enabling strictly repeatable program execution on a clock cycle-by-cycle basis.

5. The apparatus as claimed in claim 2, wherein said first circuit means comprises:

a synchronization register for providing said synchronized set of enable signals for starting operation of said IC sub-units; and

wherein said set of synchronization of enable signals occurs with a synchronization signal indicating edge alignment of all relevant functional clocks on the chip.

6. The apparatus as claimed in claim 2, wherein said first circuit means for providing configuration signals further comprises:

first and second configuration registers for providing a respective first and second set of said configuration signals;

a cycle counter for counting cycles corresponding to a slowest functional edge-aligned clock; and

,

a further multiplexer device operatively connected with said first and second configuration registers for choosing between the dual configuration registers dependent on a state of said cycle counter,

said first and second configuration registers enabling an IC processor element to reset and re-enable itself.

7. The apparatus as claimed in claim 3, wherein said second circuit means for generating a stop signal for each unique frequency clock domain comprises:

first sub-circuit for generating a clock stop command signal after a predetermined number of clock cycles of a fastest processor has elapsed; and

,

second sub-circuit responsive to said clock stop command signal for generating a clock gate signal for each unique frequency clock domain, timed such that all functional clocks can be stopped synchronously and without glitches;

wherein a program executing on a processing element in said IC is halted at a pre-determined clock cycle.

8. The apparatus as claimed in claim 7, wherein said first sub-circuit for generating a clock stop command signal comprises:

counter means responsive to said one of said synchronized set of enable signals to start counting a number of main processor IC clock cycles since a time an executing program is started;

register means for receiving a requested cycle count value; and

,

a comparison device issuing said clock stop command signal when a count of said counter means is equal to said predetermined cycle count value.

9. The apparatus as claimed in claim 8, wherein said second sub-circuit for generating a clock gate signal comprises:

means responsive to said clock stop command signal for generating a clock gate signal for each functional clock domain, timed to stop the clocks in said clock domain synchronously to the clocks in all other functional clock domains.

10. The apparatus as claimed in claim 1, further comprising:

scan-chain circuitry for scanning-out of latch logic state data values representing said IC chip logic state when said on-chip functional clocks are stopped.

11. The apparatus as claimed in claim 1, which a program recursively determines a precise cycle count in which a specific IC chip state occurs.

28. The apparatus as claimed in claim 5, wherein said synchronization register is clocked by a slowest edge-aligned clock on the chip.

12. A method for evaluating a logic state of an integrated circuit (IC), each IC including multiple processor elements for controlling operations of IC sub-units, each said IC supporting multiple synchronous frequency clock domains, said method comprising:

generating a synchronized set of enable signals in correspondence with multiple IC sub-units for starting operation of multiple IC sub-units according to a determined timing configuration;

counting, in response to one signal of said synchronized set of enable signals, a number of clock cycles of a fastest processor clock operating on said chip; and

,

upon attaining a pre-specified clock cycle number, generating a stop signal for each unique frequency clock domain associated with a different clock frequency of said multiple frequency clock domains, said stop signals output in parallel to synchronously stop a functional clock for each respective synchronous frequency clock domain; and

,

upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out logic data values for debugging a logic design flaw at a desired IC state.

13. The method as claimed in claim 12, further comprising:

providing, by a first circuit means, configuration signals for configuring operation of said IC sub-units at a determined point in time with respect to all clock edges of functional clocks at said different clock frequencies implemented in respective frequency clock domains supported by said IC.

14. The method as claimed in claim 12, wherein said determined timing configuration for starting operation of one or more IC sub-units is in synchrony with all on-chip functional clocks.

15. The method as claimed in claim 12, enabling, by said synchronized set of enable signals, strictly repeatable program execution on a clock cycle-by-cycle basis.

16. The method as claimed in claim 13, wherein said first circuit means comprises:

providing said synchronized set of enable signals from a synchronization register device, for starting operation of said IC sub-units,

wherein said synchronization set of enable signals occurs with a synchronization signal indicating edge alignment of all relevant functional clocks on the chip.

17. The method as claimed in claim 16, providing said configuration signals via one or more IC processor elements under program control.

18. The method as claimed in claim 16, wherein said first circuit means for receiving configuration signals further comprises:

providing a respective first and second set of said configuration signals from respective first and second configuration registers;

counting, by a cycle counter, synchronization cycles corresponding to a slowest functional edge-aligned clock; and

,

choosing between the first and second dual configuration registers dependent on the state of said cycle counter, wherein

said first and second configuration registers enable an IC processor element to reset and re-enable itself.

19. The method as claimed in claim 17, wherein said generating a stop signal for each unique frequency clock domain comprises:

generating a clock stop command signal after a predetermined number of main processor IC clock cycles has elapsed; and

,

generating, in response to said clock stop command signal, a clock gate signal for each unique frequency clock domain, timed such that all functional clocks can be stopped synchronously and without glitches;

wherein a program executing on a processing element in said IC is halted at a pre-determined clock cycle.

20. The method as claimed in claim 19, wherein said generating a clock stop command signal comprises:

counting, in response to receipt of one of said synchronized set of enable signals, a number of main processor IC clock cycles since a time an executing program is started;

receiving a requested cycle count value; and

,

comparing current said main processor IC clock cycle count against said requested cycle count value; and

,

issuing said clock stop command signal when said main processor IC clock cycle count is equal to said predetermined cycle count value.

21. The method as claimed in claim 19, wherein said generating a clock gate signal comprises:

implementing logic, in response to receipt of said clock stop command signal, for generating a clock gate signal for each functional clock domain, timed to stop the clocks in said clock domain synchronously to the clocks in all other functional clock domains.

22. The method as claimed in claim 12, further comprising:

scanning-out latch logic state data values representing said IC chip logic state when said on-chip functional clocks are stopped.

23. The method as claimed in claim 22, further comprising:

mapping the scan-out data obtained against predetermined design data of the chip to deduce states for each relevant latch in the IC chip.

24. The method as claimed in claim 22, further comprising:

rearranging an ordered sequence of scanned-out latch IC chip state values into a format suitable for presentation to a user.

25. The method as claimed in claim 22, further comprising:

determining a clock “

cycle-of-interest”

where IC debug commences and at which time all said on-chip functional clocks of said IC are synchronously stopped to scan out said IC latch state values, said determining including performing one or more of;

a gross linear search, a binary search, a paired binary search, or combinations thereof, to enable quick convergence on said clock cycle-of-interest.

26. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for debugging an electronic chip as claimed in claim 12.

27. The program storage device readable by a machine as claimed in claim 26, further embodying a program of instructions executable by the machine to perform method steps for

determining a clock “

cycle-of-interest”

where IC debug commences and at which time all said on-chip functional clocks of said IC are synchronously stopped to scan out said IC latch state values, said determining including performing one or more of;

a gross linear search, a binary search, a paired binary search, or combinations thereof, to enable quick convergence on said clock cycle-of-interest.

29. The method as claimed in claim 16, wherein said synchronization register is clocked by a slowest edge-aligned clock on the chip.