System for a combined error correction code and cyclic redundancy check code for a memory channel
First Claim
1. A memory system comprising:
- a memory hub device integrated in a memory module; and
a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller, wherein the link interface comprises;
first error checking and correcting (ECC) logic integrated in the link interface and first cyclic redundancy check (CRC) logic integrated in the link interface, wherein;
the external memory controller sends first data to the link interface using ECC code bits thereby setting the memory hub device into an ECC mode when a plurality of memory bits lanes in a first memory channel are not experiencing failures above a predetermined level,the external memory controller sends the first data to the link interface using CRC code bits thereby setting the memory hub device into a CRC mode when at least one of the memory bit lanes in the plurality of memory bits lanes in the first memory channel is experiencing failures above the predetermined level,responsive to receiving the first data with the ECC code bits, the first ECC logic performs error correction operations on the first data that is received from the external memory controller via the first memory channel to be transmitted to a set of memory devices,the first ECC logic generates a first error signal to the external memory controller in response to the first ECC logic detecting a first error in the first data,responsive to receiving the first data with the CRC code bits, the first CRC logic performs error detection operations on the first data that is received from the external memory controller via the first memory channel to be transmitted to the set of memory devices, andthe first CRC logic generates the first error signal to the external memory controller in response to the first CRC logic detecting the first error in the first data; and
link interface control logic integrated in the link interface, wherein the link interface control logic controls the transmission of the first data to the set of memory devices.
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Accused Products
Abstract
A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller. The link interface comprises first error correction logic integrated in the link interface that performs error correction operations on first data that is received from the external memory controller via a first memory channel to be transmitted to a set of memory devices. The first error correction logic generates a first error signal to the external memory controller in response to the first error correction logic detecting a first error in the first data. Link interface control logic integrated in the link interface controls the transmission of the first data to the set of memory devices.
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Citations
20 Claims
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1. A memory system comprising:
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a memory hub device integrated in a memory module; and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller, wherein the link interface comprises; first error checking and correcting (ECC) logic integrated in the link interface and first cyclic redundancy check (CRC) logic integrated in the link interface, wherein; the external memory controller sends first data to the link interface using ECC code bits thereby setting the memory hub device into an ECC mode when a plurality of memory bits lanes in a first memory channel are not experiencing failures above a predetermined level, the external memory controller sends the first data to the link interface using CRC code bits thereby setting the memory hub device into a CRC mode when at least one of the memory bit lanes in the plurality of memory bits lanes in the first memory channel is experiencing failures above the predetermined level, responsive to receiving the first data with the ECC code bits, the first ECC logic performs error correction operations on the first data that is received from the external memory controller via the first memory channel to be transmitted to a set of memory devices, the first ECC logic generates a first error signal to the external memory controller in response to the first ECC logic detecting a first error in the first data, responsive to receiving the first data with the CRC code bits, the first CRC logic performs error detection operations on the first data that is received from the external memory controller via the first memory channel to be transmitted to the set of memory devices, and the first CRC logic generates the first error signal to the external memory controller in response to the first CRC logic detecting the first error in the first data; and link interface control logic integrated in the link interface, wherein the link interface control logic controls the transmission of the first data to the set of memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A data processing system, comprising:
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a processor; and a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising; a memory hub device integrated in the memory module; and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller, wherein the link interface comprises; first error checking and correcting (ECC) logic integrated in the link interface and first cyclic redundancy check (CRC) logic integrated in the link interface, wherein; the external memory controller sends first data to the link interface using ECC code bits thereby setting the memory hub device into an ECC mode when a plurality of memory bits lanes in a first memory channel are not experiencing failures above a predetermined level, the external memory controller sends the first data to the link interface using CRC code bits thereby setting the memory hub device into a CRC mode when at least one of the memory bit lanes in the plurality of memory bits lanes in the first memory channel is experiencing failures above the predetermined level, responsive to receiving the first data with the ECC code bits, the first ECC logic performs error correction operations on the first data that is received from the external memory controller via the first memory channel to be transmitted to a set of memory devices, the first ECC logic generates a first error signal to the external memory controller in response to the first ECC logic detecting a first error in the first data, responsive to receiving the first data with the CRC code bits, the first CRC logic performs error detection operations on the first data that is received from the external memory controller via the first memory channel to be transmitted to the set of memory devices, and the first CRC logic generates the first error signal to the external memory controller in response to the first CRC logic detecting the first error in the first data; and link interface control logic integrated in the link interface, wherein the link interface control logic controls the transmission of the first data to the set of memory devices. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A method for performing error correction operations in a memory module, comprising:
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receiving, by a link interface in a memory hub device integrated in the memory module, an access request from an external memory controller for accessing a set of memory devices of the memory module coupled to the memory hub device, wherein the link interface error comprises error checking and correcting (ECC) logic integrated in the link interface and cyclic redundancy check (CRC) logic integrated in the link interface, wherein the external memory controller sends data to the link interface using ECC code bits thereby setting the memory hub device into an ECC mode when a plurality of memory bits lanes in a memory channel are not experiencing, failures above a predetermined level, and wherein the external memory controller sends the data to the link interface using CRC code bits thereby setting the memory hub device into a CRC mode when at least one of the memory bit lanes in the plurality of memory bits lanes in the memory channel is experiencing failures above the predetermined level; responsive to receiving the data with the ECC code bits, performing, by the ECC logic, one or more error correction operations on the data that is received from the external memory controller via the memory channel to be transmitted to the set of memory devices, wherein the ECC logic generates an error signal to the external memory controller in response to the ECC logic detecting an error in the data; responsive to receiving the data with the CRC code bits, performing, by the CRC logic, one or more error detection operations on the data that is received from the external memory controller via the memory channel to be transmitted to the set of memory devices, wherein the CRC logic generates the error signal to the external memory controller in response to the CRC logic detecting the error in the data; and controlling, by link interface control logic integrated in the link interface, the transmission of the data to the set of memory devices.
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Specification