Memory initialization time reduction

• US 8,140,937 B2
• Filed: 01/04/2008
• Issued: 03/20/2012
• Est. Priority Date: 01/04/2008
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Dasari, Shiva R., Dhawan, Sudhir, Kirscht, Joseph Allen, Vargus, Jennifer L.
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US11/969,449
• Publication Number:
  US 20090177946A1
• Time in Patent Office: 1,537 Days
• Field of Search: 714/763, 714/764, 714/766
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.

Claims

1. A computer system comprising:

a processor;

a memory further comprising a first memory unit, the first memory unit further comprising more than one memory rank;

a memory controller coupled to the processor and to the memory, the memory controller coupled to the memory unit with a rank select having a rank select signal unique to the each memory rank in the memory unit, the memory controller further comprising;

a functional encoded rank select;

an initialization encoded rank select;

a multiplexer configured to select the functional encoded rank select or the initialization encoded ranks select and output an encoded rank select;

a parity generator configured to generate a parity of the value of the encoded rank select;

an initialization control configured to, during a memory initialization period;

drive the initialization encoded rank select;

cause the multiplexer to select the initialization encoded rank select; and

cause a first rank select signal for a first memory rank and a second rank select signal for a second memory rank to be active at a particular time;

the initialization control further configured, during functional reads and writes, to cause the multiplexer to select the functional encoded rank select;

and

an error checking and correcting (ECC) unit that receives the parity from the parity generator and which generates ECC bits that are stored in a memory rank having an active rank select signal.

2. The computer system of claim 1, wherein a functional encoded rank select value of the first memory rank and a functional encoded rank select value of the second memory rank have the same parity.

3. The computer system of claim 2, the ECC unit configured to produce a particular ECC bits value for memory ranks having the same parity of their respective encoded rank select values, other inputs to the ECC being the same.

4. The computer system of claim 3, the initialization control further configured to output an initialization rank select having a number of signals equal to a number of signals as the rank select, and further configured to drive the initialization rank select on to the rank select during the initialization period.

5. The computer system of claim 1, further comprising a second memory unit wherein all memory ranks in the first memory unit have encoded rank selects having an even number of “

1”

s and all memory ranks in the second memory unit have encoded rank selects having an odd number of “

1”

s.

6. The computer system of claim 5, wherein all memory ranks in the first memory unit receive an initialization write in parallel during a first interval during the initialization period, and all memory ranks in the second memory unit receive an initialization write in parallel during a second interval during the initialization period.

7. A method of initializing multiple ranks in a memory unit of a computer, the computer having a memory controller that uses a parity of an encoded rank select in generating ECC (Error Checking and Correction) bits during writes to a memory unit having a plurality of memory ranks, the method comprising:

selecting, during a first interval in an initialization period, a first set of more than one memory ranks in a memory unit, each memory rank in the first set having an encoded rank select having an even number of “

1”

s;

writing initialization data, including ECC bits, to the first set of more than one memory ranks in the memory unit;

selecting, during a second interval in the initialization period, a second set of more than one memory ranks in a memory unit, each memory rank in the second set having an encoded rank select having an odd number of “

1”

s; and

writing initialization data, including ECC bits, to the second set of more than one memory ranks in the memory unit.

8. The method of claim 7, further comprising:

using a first initialization encoded rank select having an even number of “

1”

s to create the parity during the first interval; and

using a second initialization encoded rank select having an odd number of “

1”

s to create the parity during the second interval.

9. The method of claim 8, further comprising, during functional writes, using a functional encoded rank select to create the parity.

10. The method of claim 9, further comprising checking of ECC by the memory controller on data read from the memory unit.