Hard component failure detection and correction

• US 8,140,945 B2
• Filed: 05/23/2008
• Issued: 03/20/2012
• Est. Priority Date: 05/23/2008
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Cypher, Robert E.
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US12/126,325
• Publication Number:
  US 20090292968A1
• Time in Patent Office: 1,397 Days
• Field of Search: 714/758, 714/785
• US Class Current: 714/785
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/22 using redundant apparatus to increase reliability
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links

Abstract

In one embodiment, a memory controller comprises a check bit encoder circuit coupled to receive a data block to be written to memory, a check/correct circuit coupled to receive an encoded data block read from the memory, and a hard failure detection circuit coupled to the check/correct circuit. The check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits. The check/correct circuit is configured to detect an error in the encoded data block responsive to the first check bits, the second check bits, and the data block within the encoded data block, which is logically arranged as an array of R rows and N columns, wherein R and N are positive integers. Each of the first check bits covers a respective row of the array, and the check/correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits. A presence of more than one binary one in the first syndrome indicates a multi-bit error. Responsive to detecting the multi-bit error, the hard failure detection circuit is configured to perform a plurality of memory read/write operations to the memory locations in which the encoded data block is stored to identify a hard error failure in the memory.

Claims

1. A memory controller comprising:

a check bit encoder circuit coupled to receive a data block to be written to memory, wherein the check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits; and

a check/correct circuit coupled to receive an encoded data block read from the memory, the check/correct circuit configured to detect an error in the encoded data block responsive to the first plurality of check bits, the second plurality of check bits, and the data block within the encoded data block, and wherein the encoded data block is logically arranged as an array of R rows and N columns, wherein R and N are positive integers, and wherein each of the first plurality of check bits covers a respective row of the array, and wherein the check/correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits, and wherein a presence of more than one binary one in the first syndrome indicates a multi-bit error; and

a hard failure detection circuit coupled to the check/correct circuit wherein, responsive to detecting the multi-bit error, the hard failure detection circuit is configured to perform a plurality of memory read/write operations to the memory locations in which the encoded data block is stored to identify a hard error failure in the memory.

2. The memory controller as recited in claim 1 wherein the plurality of memory read/write operations includes at least one write that updates the memory locations with different data than the encoded data block.

3. The memory controller as recited in claim 2 wherein the at least one write updates the memory locations with the complement of the encoded data block.

4. The memory controller as recited in claim 3 wherein the plurality of memory operations includes at least one read operation to read the complement of the encoded data block.

5. The memory controller as recited in claim 4 wherein the hard failure detection circuit is configured to logically combine the encoded data block and the complement of the encoded data block to identify the hard error failure.

6. The memory controller as recited in claim 5 wherein the logical combination comprises exclusive NOR (XNOR), and wherein each binary one bit in a result of the XNOR indicates a hard failure bit.

7. The memory controller as recited in claim 6 wherein the memory comprises a plurality of memory devices, and wherein, responsive to all the hard failure bits being located in the same memory device of the plurality of memory devices, the error check/correct circuit is configured to correct the hard error in the data block and provide the corrected data block.

8. The memory controller as recited in claim 1 wherein the first plurality of check bits form a first column of the array, and wherein the second plurality of check bits are stored in a second column of the array and are defined to cover bits in the array according to a plurality of check vectors, each of the plurality of check vectors corresponding to a different bit in the array, and each of the plurality of check vectors is an element of a Galois Field (GF(2^X)), and wherein X is a positive integer equal to a number of the second plurality of bits, and wherein the plurality of check vectors are derived from a plurality of unique elements of GF(2^X), each of the plurality of unique elements corresponding to a different column of the array, and wherein each of the plurality of unique elements includes at least one non-zero bit, including the element corresponding to the first column of the array, and wherein the check vector in row Z of the column is the product, in GF(2^X) of the unique element for that column and alpha^Z, wherein alpha is a primitive element of GF(2^X).

9. The memory controller as recited in claim 8 wherein if the first syndrome, when viewed as an element of GF(2^X), is non-zero, the hard failure detection circuit is configured to inhibit performing the hard error failure detection.

10. A method comprising:

reading an encoded data block from memory, wherein the encoded data block comprises a data block, a first plurality of check bits, and a second plurality of check bits;

detecting an error in the encoded data block responsive to the first plurality of check bits, the second plurality of check bits, and the data block within the encoded data block, wherein the encoded data block is logically arranged as an array of R rows and N columns, wherein R and N are positive integers, and wherein each of the first plurality of check bits covers a respective row of the array, and wherein detecting the error comprises generating a first syndrome corresponding to the first plurality of check bits, and wherein a presence of more than one binary one in the first syndrome indicates a multi-bit error; and

responsive to detecting the multi-bit error, identifying a hard failure in the memory by performing a plurality of memory read/write operations to the memory locations in which the encoded data block is stored.

11. The method as recited in claim 10 wherein the plurality of memory read/write operations includes at least one write that updates the memory locations with different data than the encoded data block.

12. The method as recited in claim 11 wherein the at least one write updates the memory locations with the complement of the encoded data block.

13. The method as recited in claim 12 wherein the plurality of memory operations includes at least one read operation to read the complement of the encoded data block.

14. The method as recited in claim 13 wherein identifying the hard failure comprises logically combining the encoded data block and the complement of the encoded data block.

15. The method as recited in claim 14 wherein the logically combining comprises exclusive NORing (XNORing), and wherein each binary one bit in a result of the XNOR indicates a hard failure bit.

16. The method as recited in claim 15 wherein the memory comprises a plurality of memory devices, and method comprises:

determining that all the hard failure bits are located in the same memory device of the plurality of memory devices; and

correcting the hard error in the data block and provide the corrected data block.

17. The method as recited in claim 10 wherein the first plurality of check bits form a first column of the array, and wherein the second plurality of check bits are stored in a second column of the array and are defined to cover bits in the array according to a plurality of check vectors, each of the plurality of check vectors corresponding to a different bit in the array, and each of the plurality of check vectors is an element of a Galois Field (GF(2^X)), and wherein X is a positive integer equal to a number of the second plurality of bits, and wherein the plurality of check vectors are derived from a plurality of unique elements of GF(2^X), each of the plurality of unique elements corresponding to a different column of the array, and wherein each of the plurality of unique elements includes at least one non-zero bit, including the element corresponding to the first column of the array, and wherein the check vector in row Z of the column is the product, in GF(2^X) of the unique element for that column and alpha^Z, wherein alpha is a primitive element of GF(2^X).

18. The method as recited in claim 17 further comprising:

reading a second encoded data block from memory;

generating a second syndrome corresponding to the first plurality of check bits and the second encoded data block; and

viewing the second syndrome as an element of GF(2^X), and wherein, responsive to detecting that the second syndrome is non-zero in GF(2^X), not attempting to identify a hard error failure for the second encoded data block.