Integrated circuit packaging system substrates and method of manufacture thereof

• US 8,143,107 B2
• Filed: 03/02/2010
• Issued: 03/27/2012
• Est. Priority Date: 08/03/2007
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Do, Byung Tai, Shim, Il Kwon, Chow, Seng Guan
• Primary Examiner(s): Dang, Phuc
• Application Number:
  US12/715,910
• Publication Number:
  US 20100155926A1
• Time in Patent Office: 756 Days
• Field of Search: 257/690, 257/691, 257/713, 257/776, 257/790, 257/E21.499, 361/777, 361/778, 361/794, 438/124, 438/126, 438/127
• US Class Current: 438/124
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.

Claims

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a substrate including;

patterning a bonding pad directly contacting the substrate,

patterning a first signal trace coupled to the bonding pad, and

patterning a second signal trace directly contacting the substrate;

mounting an integrated circuit directly contacting the substrate; and

coupling an electrical interconnect between the integrated circuit, the bonding pad, or a combination thereof.

2. The method as claimed in claim 1 further comprising forming a staggered second row of the bonding pads for connecting the integrated circuit.

3. The method as claimed in claim 1 wherein forming the substrate includes:

forming the first signal trace directly contacting the substrate;

forming the second signal trace adjacent to the first signal trace;

connecting a pedestal directly contacting the second signal trace; and

positioning the bonding pad, coupled to the first signal trace, in line with the pedestal.

4. The method as claimed in claim 1 further comprising forming an integrated circuit package by encapsulating the substrate, the integrated circuit, and the electrical interconnect.

5. A method of manufacture of an integrated circuit packaging system comprising:

forming a substrate including;

patterning a bonding pad directly contacting the substrate by applying a foil,

patterning a first signal trace coupled to the bonding pad by plating the first signal trace,

patterning a second signal trace directly contacting the substrate adjacent to the first signal trace, and

connecting a pedestal directly contacting the second signal trace having a staggered position from the bonding pad;

mounting an integrated circuit directly contacting the substrate includes mounting an integrated circuit having a fine pitch array of the contact pads; and

coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.

6. The method as claimed in claim 5 wherein connecting a pedestal includes:

forming a ball bond on the second signal trace includes positioning the ball bond in a staggered array; and

coining the ball bond for creating a flat surface.

7. The method as claimed in claim 5 further comprising forming a staggered second row of the bonding pad for connecting the integrated circuit including positioning the staggered second row in the gaps of a first row.

8. The method as claimed in claim 5 wherein forming the substrate includes:

forming the first signal trace on the substrate;

forming the second signal trace adjacent to the first signal trace;

mounting the pedestal on the second signal trace; and

positioning the bonding pad, coupled to the first signal trace, in line with the pedestal including coupling an electrical interconnect having a vertical clearance form the bonding pad.

9. The method as claimed in claim 5 further comprising forming an integrated circuit package by encapsulating the substrate, the integrated circuit, and the electrical interconnect including assembling a printed circuit board with the integrated circuit package.

10. An integrated circuit packaging system comprising:

a substrate including;

a bonding pad directly contacting the substrate,

a first signal trace coupled to the bonding pad, and

a second signal trace directly contacting the substrate;

an integrated circuit mounted directly contacting the substrate; and

an electrical interconnect coupled between the integrated circuit, the bonding pad, or a combination thereof.

11. The system as claimed in claim 10 further comprising a staggered second row of the bonding pad for connecting the integrated circuit.

12. The system as claimed in claim 10 wherein the substrate includes:

the first signal trace directly contacting the substrate;

the second signal trace adjacent to the first signal trace;

a pedestal directly contacting the second signal trace; and

the bonding pad, coupled to the first signal trace, in line with the pedestal.

13. The system as claimed in claim 10 further comprising an integrated circuit package formed by the substrate, the integrated circuit, and the electrical interconnect encapsulated.

14. The system as claimed in claim 10 wherein:

the substrate includes;

the bonding pad formed of a thin foil,

the first signal trace, coupled to the bonding pad, plated,

the second signal trace directly contacting the substrate adjacent to the first signal trace, and

a pedestal directly contacting the second signal trace having a staggered position from the bonding pad;

the integrated circuit mounted en directly contacting the substrate includes the integrated circuit having a line pitch array or the contact pad; and

the electrical interconnect coupled between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.

15. The system as claimed in claim 14 wherein the pedestal includes:

a ball bond on the second signal trace includes the ball bond positioned in a staggered array; and

the ball bond coined for creating a flat surface.

16. The system as claimed in claim 14 further comprising a staggered second row of the bonding pad for connecting the integrated circuit includes the staggered second row positioned in the gaps of the first row.

17. The system as claimed in claim 14 wherein the substrate includes:

the first signal trace on the substrate;

the second signal trace adjacent to the first signal trace;

the pedestal on the second signal trace; and

the bonding pad, coupled to the first signal trace, positioned in line with the pedestal includes an electrical interconnect having a vertical clearance form the bonding pad.

18. The system as claimed in claim 14 further comprising an integrated circuit package formed by the substrate, the integrated circuit, and the electrical interconnect encapsulated includes a printed circuit board assembled with the integrated circuit package.