Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices

• US 8,143,123 B2
• Filed: 03/03/2008
• Issued: 03/27/2012
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Grebs, Thomas E., Ridley, Rodney S., Sapp, Steven P., Wilson, Peter H., Sani, Babak S., Dolny, Gary M., Mytych, John, Losee, Becky, Selsley, Adam, Kocon, Christopher B.
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US12/041,546
• Publication Number:
  US 20080199997A1
• Time in Patent Office: 1,485 Days
• Field of Search: 438/270, 438/283, 438/259
• US Class Current: 438/259
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.

Claims

1. A process for forming an inter-electrode dielectric layer inside a trench, comprising:

lining sidewalls and bottom of the trench with a first layer of dielectric material;

substantially filling the trench with a first layer of conductive material to form a first electrode;

recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench forming shallow troughs on the top surface of the first dielectric layer remaining on either side of the conductive material;

forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench;

oxidizing the layer of polysilicon material thereby converting it into a silicon dioxide layer; and

forming a second electrode made of conductive material inside the trench atop the silicon dioxide and isolated from trench sidewalls by a second dielectric layer.

2. A process for forming an inter-electrode dielectric layer inside a trench, comprising:

lining sidewalls and bottom of the trench with a first layer of dielectric material;

substantially filling the trench with a first layer of conductive material to form a first electrode;

recessing the first layer of conductive material to a first depth inside the trench;

substantially filling a remaining portion of the trench with dielectric fill material;

recessing the first layer of dielectric material and the dielectric fill material to a second depth to form an inter-electrode dielectric layer; and

forming a second electrode made of conductive material inside the trench atop the inter-electrode dielectric layer and isolated from trench sidewalls by a second dielectric layer.

3. A process for forming an inter-electrode dielectric layer inside a trench, comprising:

lining sidewalls and bottom of the trench with a first layer of dielectric material;

substantially filling the trench with a first layer of conductive material to form a first electrode;

recessing the first layer of conductive material to a first depth inside the trench such that a top portion of the recessed conductive material is higher than a final target depth by a desired thickness;

enhancing an oxidation rate of the top portion of the recessed first layer of conductive material;

removing the first layer of dielectric material from remaining trench sidewalls;

performing an oxidation step whereby the altered top portion of the first layer of conductive material oxidizes at a faster rate than the trench sidewalls, forming an inter-electrode dielectric layer that is thicker than sidewall dielectric lining; and

forming a second electrode made of conductive material inside the trench atop the inter-electrode dielectric layer and isolated from trench sidewalls by the sidewall dielectric lining.

4. The method of claim 3 wherein the step of enhancing an oxidation rate of the top portion of the recessed first layer of conductive material comprises one of either chemically or physically altering the top portion.

5. The method of claim 3 wherein the step of enhancing an oxidation rate of the top portion of the recessed first layer of conductive material comprises implanting impurities substantially perpendicularly to a top surface of the first layer of conductive material.

6. The method of claim 5 wherein the impurities are one of argon or fluorine.

7. A method for forming an inter-electrode dielectric layer inside a trench, comprising:

lining sidewalls and bottom of the trench with a first layer of dielectric material;

substantially filling the trench with a first layer of conductive material to form a first electrode;

recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench;

preferentially forming a second layer of dielectric whereby a relatively thicker inter-electrode dielectric layer is formed on horizontal surface structure inside the trench and a relatively thin dielectric layer is formed along sidewalls of the trench;

removing the relatively thin dielectric layer along sidewalls of the trench; and

forming a second electrode made of conductive material inside the trench atop the inter-electrode dielectric layer and isolated from trench sidewalls by a sidewall dielectric lining.

8. The method of claim 7 wherein the step of preferentially forming a second dielectric layer comprises a directional deposition process.

9. The method of claim 8 wherein the directional deposition process comprises plasma-enhanced chemical vapor deposition.

10. A method forming an inter-electrode dielectric layer inside a trench, comprising:

lining sidewalls and bottom of the trench with a first layer of dielectric material;

substantially filling the trench with a first layer of conductive material to form a first electrode;

recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench;

forming a thin layer of screen oxide along vertical and horizontal surfaces inside the trench;

forming a layer of silicon nitride covering the thin layer of screen oxide;

removing the silicon nitride from the bottom of the trench to expose the horizontal layer of screen oxide but leaving the vertical screen oxide covered by the silicon nitride;

exposing the trench to an oxidizing ambient to form a relatively thick inter-electrode dielectric layer on the horizontal bottom surface of the trench;

removing the silicon nitride from trench sidewalls; and

forming a second electrode made of conductive material inside the trench atop the inter-electrode dielectric layer and isolated from trench sidewalls by a sidewall dielectric lining.

11. A method for forming an inter-electrode dielectric layer inside a trench formed in a semiconductor substrate, comprising:

forming a first electrode made of conductive material in a lower portion of the trench and isolated from trench sidewalls and bottom by a first dielectric lining;

forming a thick layer of dielectric material filling the trench and extending above the semiconductor substrate;

substantially planarizing the thick layer of dielectric layer back to a top surface of the semiconductor substrate; and

performing an isotropic wet etch process that recesses the remaining portion of the thick layer of dielectric material inside the trench to a target depth.

12. The method of claim 11 wherein the step of substantially planarizing comprises performing an anisotropic plasma etch process.

13. The method of claim 11 wherein the step of substantially planarizing comprises performing a chemical mechanical planarization process.

14. A method for forming a semiconductor device, comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region,

lining sidewalls and bottom of the active trench with a first layer of dielectric material;

substantially filling the active trench with a first layer of conductive material to form a first electrode;

recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench;

forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench;

oxidizing the layer of polysilicon material thereby converting it into a silicon dioxide layer;

forming a second electrode made of conductive material inside the trench atop the silicon dioxide and isolated from trench sidewalls by a second dielectric layer;

forming a plurality of source regions having the first conductivity type in the well region adjacent the active trench;

forming a charge control trench extending deeper into the drift region than the active trench;

lining the charge control trench with a layer of dielectric material; and

depositing in the lined charge control trench a conductive material to allow for vertical charge control in the drift region.

15. The method of claim 14 further comprising forming independent electrical contacts for the first electrode and the second electrode to independently electrically bias each electrode.

16. The method of claim 14 wherein the lined charge control trench is substantially filled with the conductive material.

17. The method of claim 14 further comprising disposing inside the charge control trench a plurality of conductive layers stacked vertically and separated from each other and from the charge control trench sidewalls by a dielectric material.

18. The method of claim 17 further comprising forming independent electrical contacts for the plurality of conductive layers.

19. The method of claim 17 further comprising varying the thicknesses of the plurality of the conductive layers.